1 /* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_ 9 10 #define WIFI_MAC_INTR_SOURCE 0 11 #define WIFI_MAC_NMI_SOURCE 1 12 #define WIFI_PWR_INTR_SOURCE 2 13 #define WIFI_BB_INTR_SOURCE 3 14 #define BT_MAC_INTR_SOURCE 4 15 #define BT_BB_INTR_SOURCE 5 16 #define BT_BB_NMI_SOURCE 6 17 #define LP_TIMER_SOURCE 7 18 #define COEX_SOURCE 8 19 #define BLE_TIMER_SOURCE 9 20 #define BLE_SEC_SOURCE 10 21 #define I2C_MASTER_SOURCE 11 22 #define APB_CTRL_INTR_SOURCE 12 23 #define GPIO_INTR_SOURCE 13 24 #define GPIO_NMI_SOURCE 14 25 #define SPI1_INTR_SOURCE 15 26 #define SPI2_INTR_SOURCE 16 27 #define UART0_INTR_SOURCE 17 28 #define UART1_INTR_SOURCE 18 29 #define LEDC_INTR_SOURCE 19 30 #define EFUSE_INTR_SOURCE 20 31 #define RTC_CORE_INTR_SOURCE 21 32 #define I2C_EXT0_INTR_SOURCE 22 33 #define TG0_T0_LEVEL_INTR_SOURCE 23 34 #define TG0_WDT_LEVEL_INTR_SOURCE 24 35 #define CACHE_IA_INTR_SOURCE 25 36 #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26 37 #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27 38 #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28 39 #define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29 40 #define ICACHE_PRELOAD0_INTR_SOURCE 30 41 #define ICACHE_SYNC0_INTR_SOURCE 31 42 #define APB_ADC_INTR_SOURCE 32 43 #define DMA_CH0_INTR_SOURCE 33 44 #define SHA_INTR_SOURCE 34 45 #define ECC_INTR_SOURCE 35 46 #define FROM_CPU_INTR0_SOURCE 36 47 #define FROM_CPU_INTR1_SOURCE 37 48 #define FROM_CPU_INTR2_SOURCE 38 49 #define FROM_CPU_INTR3_SOURCE 39 50 #define ASSIST_DEBUG_INTR_SOURCE 40 51 #define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41 52 #define CACHE_CORE0_ACS_INTR_SOURCE 42 53 54 /* RISC-V supports priority values from 1 (lowest) to 15. 55 * As interrupt controller for Xtensa and RISC-V is shared, this is 56 * set to an intermediate and compatible value. 57 */ 58 #define IRQ_DEFAULT_PRIORITY 3 59 60 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 61 62 #endif 63
