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Searched refs:UART0_INTR_SOURCE (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h27 #define UART0_INTR_SOURCE 17 macro
Desp-esp32c3-intmux.h31 #define UART0_INTR_SOURCE 21 macro
Desp-xtensa-intmux.h44 #define UART0_INTR_SOURCE 34 /* UART0, level */ macro
Desp-esp32c6-intmux.h53 #define UART0_INTR_SOURCE 43 /* interrupt of UART0, level*/ macro
Desp32s3-xtensa-intmux.h36 #define UART0_INTR_SOURCE 27 /* interrupt of UART0, level*/ macro
Desp32s2-xtensa-intmux.h47 #define UART0_INTR_SOURCE 37 /* UART0, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi151 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi234 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi198 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi157 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi217 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi203 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;