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Searched refs:TG0_WDT_LEVEL_INTR_SOURCE (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h34 #define TG0_WDT_LEVEL_INTR_SOURCE 24 macro
Desp-esp32c3-intmux.h43 #define TG0_WDT_LEVEL_INTR_SOURCE 33 macro
Desp-xtensa-intmux.h26 #define TG0_WDT_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, WATCHDOG, level */ macro
Desp-esp32c6-intmux.h63 #define TG0_WDT_LEVEL_INTR_SOURCE 53 /* interrupt of TIMER_GROUP0, WATCH DOG, level*/ macro
Desp32s3-xtensa-intmux.h58 #define TG0_WDT_LEVEL_INTR_SOURCE 52 /* interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ macro
Desp32s2-xtensa-intmux.h27 #define TG0_WDT_LEVEL_INTR_SOURCE 17 /* TIMER_GROUP0, WATCHDOG, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi206 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi161 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi282 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi319 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi356 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi444 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;