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Searched refs:I2C_EXT0_INTR_SOURCE (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h32 #define I2C_EXT0_INTR_SOURCE 22 macro
Desp-esp32c3-intmux.h39 #define I2C_EXT0_INTR_SOURCE 29 macro
Desp-xtensa-intmux.h60 #define I2C_EXT0_INTR_SOURCE 49 /* I2C controller1, level */ macro
Desp-esp32c6-intmux.h60 #define I2C_EXT0_INTR_SOURCE 50 /* interrupt of I2C controller1, level*/ macro
Desp32s3-xtensa-intmux.h49 #define I2C_EXT0_INTR_SOURCE 42 /* interrupt of I2C controller1, level*/ macro
Desp32s2-xtensa-intmux.h62 #define I2C_EXT0_INTR_SOURCE 52 /* I2C controller1, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi141 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi224 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi174 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi228 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi330 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi279 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;