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/Zephyr-latest/soc/st/stm32/stm32h7x/
Dsections.ld20 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2)));
22 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 256;
24 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 16K;
25 …_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram2)), LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(…
Dmpu_regions.c34 DT_REG_ADDR(DT_NODELABEL(sram2)),
37 DT_REG_ADDR(DT_NODELABEL(sram2)),
/Zephyr-latest/tests/application_development/code_relocation/src/
Dtest_file1.c18 __in_section(data, sram2, var) uint32_t var_sram2_data = 10U;
19 __in_section(bss, sram2, var) uint32_t var_sram2_bss;
21 __in_section(rodata, sram2, var) const uint32_t var_sram2_rodata = 100U;
43 /* Print values from sram2 */ in ZTEST()
52 "var_sram2_data not in sram2 region"); in ZTEST()
Dtest_file4.c11 __in_section(data, sram2, var) uint32_t var_file4_sram2_data = 10U;
12 __in_section(bss, sram2, var) uint32_t var_file4_sram2_bss; in __in_section() argument
Dtest_file5.c11 __in_section(data, sram2, var) uint32_t var_file5_sram2_data = 10U;
12 __in_section(bss, sram2, var) uint32_t var_file5_sram2_bss; in __in_section() argument
/Zephyr-latest/doc/kernel/
Dcode-relocation.rst22 ``SRAM2:/home/xyz/zephyr/samples/hello_world/src/main.c,SRAM1:/home/xyz/zephyr/samples/hello_world/…
57 ``zephyr_code_relocate(FILES src/*.c LOCATION SRAM2)``
71 * if the memory is SRAM1, SRAM2, CCD, or AON, then place the full object in the
76 zephyr_code_relocate(FILES src/file1.c LOCATION SRAM2)
89 This will place data and bss inside SRAM2.
114 sections of ``file1.c`` will not stick to SRAM2.
138 snippet will relocate serial drivers to SRAM2:
142 zephyr_code_relocate(LIBRARY drivers__serial LOCATION SRAM2)
/Zephyr-latest/tests/application_development/code_relocation/
DCMakeLists.txt18 zephyr_code_relocate(FILES src/test_file1.c ${SRAM2_PHDR} LOCATION SRAM2)
27 zephyr_code_relocate(LIBRARY test_lib LOCATION SRAM2)
33 zephyr_code_relocate(FILES ${genex_expr} LOCATION SRAM2)
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dmax32662evkit.overlay7 /* Increase SRAM2 size to get enough space for image */
8 &sram2 {
/Zephyr-latest/dts/arm/st/u0/
Dstm32u031X4.dtsi17 sram2: memory@20080000 { label
20 zephyr,memory-region = "SRAM2";
Dstm32u031X6.dtsi17 sram2: memory@20080000 { label
20 zephyr,memory-region = "SRAM2";
Dstm32u031X8.dtsi17 sram2: memory@20080000 { label
20 zephyr,memory-region = "SRAM2";
Dstm32u083Xc.dtsi17 sram2: memory@20008000 { label
20 zephyr,memory-region = "SRAM2";
Dstm32u073.dtsi74 sram2: memory@20008000 { label
76 zephyr,memory-region = "SRAM2";
/Zephyr-latest/dts/arm/st/h5/
Dstm32h533Xe.dtsi16 sram2: memory@20040000 { label
19 zephyr,memory-region = "SRAM2";
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4r5.dtsi11 /delete-node/ &sram2; /* different memory address */
21 sram2: memory@20040000 { label
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/
DKconfig62 bool "Clock LPC54XXX SRAM2"
65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
/Zephyr-latest/tests/application_development/code_relocation/test_lib/
Dtest_lib1.c11 __in_section(data, sram2, var) uint32_t var_lib1_sram2_data = 10U;
12 __in_section(bss, sram2, var) uint32_t var_lib1_sram2_bss; in __in_section() argument
/Zephyr-latest/tests/drivers/memc/ram/src/
Dmain.c44 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram2))
45 BUF_DEF(sram2);
96 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram2)) in ZTEST()
/Zephyr-latest/tests/drivers/spi/spi_loopback/
Doverlay-stm32-spi-dma-dt-nocache-mem.conf7 CONFIG_DT_DEFINED_NOCACHE_NAME="SRAM2"
Doverlay-stm32-spi-16bits-dma-dt-nocache-mem.conf13 CONFIG_DT_DEFINED_NOCACHE_NAME="SRAM2"
/Zephyr-latest/soc/espressif/esp32/
Dmemory.h21 /* SRAM2 (200kB) data memory */
22 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))
23 #define SRAM2_DRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram2))
/Zephyr-latest/soc/espressif/esp32s3/
Dmemory.h7 /* SRAM0 (32k), SRAM1 (416k), SRAM2 (64k) memories
16 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))
17 #define SRAM2_SIZE DT_REG_SIZE(DT_NODELABEL(sram2))
/Zephyr-latest/samples/boards/intel/adsp/code_relocation/
Dlinker_xtensa_intel_adsp_cavs.ld13 /* Use SRAM2 for TEXT, SRAM3 for DATA and SRAM4 for BSS.
18 * |Reserved | SRAM4 | SRAM2 | SRAM0 | SRAM3 |
44 SRAM2 (wx) : ORIGIN = (SRAM2_ADDR), LENGTH = RAM_SIZE2
/Zephyr-latest/dts/arm/st/h7/
Dstm32h743.dtsi78 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
79 sram2: memory@30020000 { label
82 zephyr,memory-region = "SRAM2";
/Zephyr-latest/samples/subsys/display/lvgl/boards/
Dmax32662evkit.overlay14 * Concatenate SRAM0(16KB), SRAM1(16KB) and SRAM2(16KB)

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