1/*
2 * Copyright (c) 2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/linker/sections.h>
8#include <zephyr/devicetree.h>
9
10#include <zephyr/linker/linker-defs.h>
11#include <zephyr/linker/linker-tool.h>
12
13/* Use SRAM2 for TEXT, SRAM3 for DATA and SRAM4 for BSS.
14 * To ensure they are contiguous (and compatible with default SRAM
15 * usage), they are laid out like this:
16 *
17 *  *---------------------------------------------------------------*
18 *  |Reserved |    SRAM4    |    SRAM2    |     SRAM0     |  SRAM3  |
19 *  *---------------------------------------------------------------*
20 *  |         |     BSS     |         TEXT         |     DATA       |
21 *  *---------------------------------------------------------------*
22 *
23 * Note that BSS, TEXT and DATA are contiguous, but that SRAM0 (default
24 * RAM) has a bit of both TEXT and DATA. In fact, the default linker
25 * script would also place some BSS section on SRAM0, which would break
26 * the contiguousness. To avoid that, before including the platform
27 * default linker script, all BSS content is put in the SRAM4 region.
28 * (More info at the comment before SECTIONS below.)
29 *
30 * One final detail: SRAM4 actually lives in the "uncached" memory,
31 * but `fix_elf_addrs.py` will place it as above for rimage.
32 */
33#define SRAM2_ADDR  (DT_REG_ADDR(DT_NODELABEL(sram0)) + 32 * 1024)
34#define RAM_SIZE2 (CONFIG_HP_SRAM_RESERVE - 32 * 1024)
35
36#define SRAM3_ADDR  (DT_REG_ADDR(DT_NODELABEL(sram3)))
37#define RAM_SIZE3  (DT_REG_SIZE(DT_NODELABEL(sram3)))
38
39#define SRAM4_ADDR  ((DT_REG_ADDR(DT_NODELABEL(sram0)) - 512 * 1024 * 1024) + 16 * 1024)
40#define RAM_SIZE4  (16 * 1024)
41
42MEMORY
43{
44  SRAM2                  (wx) : ORIGIN = (SRAM2_ADDR), LENGTH = RAM_SIZE2
45  SRAM3                  (wx) : ORIGIN = (SRAM3_ADDR), LENGTH = RAM_SIZE3
46  SRAM4                  (wx) : ORIGIN = (SRAM4_ADDR), LENGTH = RAM_SIZE4
47}
48
49#define MPU_ALIGN(region_size) \
50    . = ALIGN(4)
51
52/* Place all of BSS content in SRAM4. If not done this way, platform default
53 * linker script would add them after DATA, thus breaking contiguousness.
54 * Note that an empty BSS section will still be generated during build, but
55 * is ignored by `fix_elf_addrs.py` when generating artifacts for rimage.
56 */
57SECTIONS {
58  .bss (NOLOAD) :
59  {
60    . = ALIGN(64);
61    _bss_start = .;
62    *(.dynsbss)
63    *(.sbss)
64    *(.sbss.*)
65    *(.gnu.linkonce.sb.*)
66    *(.scommon)
67    *(.sbss2)
68    *(.sbss2.*)
69    *(.gnu.linkonce.sb2.*)
70    *(.dynbss)
71    *(.bss)
72    *(.bss.*)
73    *(.gnu.linkonce.b.*)
74    *(COMMON)
75  #ifdef CONFIG_CODE_DATA_RELOCATION
76  #include <linker_sram_bss_relocate.ld>
77  #endif
78    . = ALIGN(8);
79    _bss_end = .;
80  } >SRAM4
81}
82
83#include <xtensa-cavs-linker.ld>
84