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Searched +full:osc +full:- +full:freq (Results 1 – 23 of 23) sorted by relevance

/Zephyr-latest/dts/bindings/can/
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
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Dmicrochip,mcp2515.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [spi-device.yaml, can-controller.yaml]
11 osc-freq:
15 int-gpios:
16 type: phandle-array
/Zephyr-latest/boards/shields/mikroe_mcp2518fd_click/
Dmikroe_mcp2518fd_click.overlay2 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
8 spi-max-frequency = <18000000>;
9 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
11 osc-freq = <40000000>;
/Zephyr-latest/boards/shields/mcp2515/
Dadafruit_can_picowbell.overlay4 * SPDX-License-Identifier: Apache-2.0
9 cs-gpios = <&pico_header 20 GPIO_ACTIVE_LOW>;
13 spi-max-frequency = <1000000>;
14 int-gpios = <&pico_header 21 GPIO_ACTIVE_LOW>;
17 osc-freq = <16000000>;
19 can-transceiver {
20 max-bitrate = <1000000>;
Ddfrobot_can_bus_v2_0.overlay4 * SPDX-License-Identifier: Apache-2.0
9 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
13 spi-max-frequency = <1000000>;
14 int-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */
17 osc-freq = <16000000>;
19 can-transceiver {
20 min-bitrate = <60000>;
21 max-bitrate = <1000000>;
Dkeyestudio_can_bus_ks0411.overlay4 * SPDX-License-Identifier: Apache-2.0
9 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
13 spi-max-frequency = <1000000>;
14 int-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
17 osc-freq = <16000000>;
19 can-transceiver {
20 max-bitrate = <1000000>;
/Zephyr-latest/drivers/counter/
Dcounter_smartbond_timer.c4 * SPDX-License-Identifier: Apache-2.0
37 uint32_t freq; member
87 const struct counter_smartbond_config *config = dev->config; in counter_smartbond_is_sleep_allowed()
90 (dev == COUNTER_DT_DEVICE(2))) && !config->clock_src_divn); in counter_smartbond_is_sleep_allowed()
96 const struct counter_smartbond_config *config = dev->config; in counter_smartbond_pdc_trigger_get()
98 switch ((uint32_t)config->timer) { in counter_smartbond_pdc_trigger_get()
119 struct counter_smartbond_data *data = dev->data; in counter_smartbond_pdc_add()
122 data->pdc_idx = da1469x_pdc_add(trigger, MCU_PDC_MASTER_M33, PDC_XTAL_EN); in counter_smartbond_pdc_add()
123 __ASSERT_NO_MSG(data->pdc_idx >= 0); in counter_smartbond_pdc_add()
125 da1469x_pdc_set(data->pdc_idx); in counter_smartbond_pdc_add()
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/Zephyr-latest/soc/nxp/mcx/mcxw/
Dsoc.c2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
53 /* Re-enable monitor */ in clock_init()
98 /* OSC-RF / System Oscillator Configuration */ in clock_init()
100 .freq = 32000000U, in clock_init()
105 /* Init OSC-RF / SOSC */ in clock_init()
107 CLOCK_SetXtal0Freq(sosc_config.freq); in clock_init()
200 base->STATUSA |= VBAT_STATUSA_POR_DET_MASK; in vbat_init()
/Zephyr-latest/dts/arm/renesas/smartbond/
Dda1469x.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <arm/armv8-m.dtsi>
8 #include <freq.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/adc/smartbond-adc.h>
11 #include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
12 #include <zephyr/dt-bindings/dma/dma_smartbond.h>
17 zephyr,flash-controller = &flash_controller;
21 compatible = "zephyr,lvgl-pointer-input";
25 #address-cells = <1>;
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/Zephyr-latest/boards/phytec/phyboard_polis/
Dphyboard_polis_mimx8mm6_m4.dts2 * Copyright (c) 2022-2024 PHYTEC Messtechnik GmbH
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "phyboard_polis-pinctrl.dtsi"
13 model = "phyBOARD-Polis i.MX8M Mini";
17 uart-4 = &uart4;
18 uart-3 = &uart3;
19 uart-2 = &uart2;
20 uart-1 = &uart1;
28 zephyr,shell-uart = &uart4;
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/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c2 * Copyright 2021-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
33 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \
72 "ARM PLL must have clock-mult property");
74 "ARM PLL must have clock-div property");
174 if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { in clock_init()
190 if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & in clock_init()
196 if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & in clock_init()
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/Zephyr-latest/soc/nxp/mcx/mcxc/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
21 #define OSC_NODE DT_NODELABEL(osc)
30 #define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
56 /* Low-frequency Reference Clock Divider */
58 /* Second Low-frequency Reference Clock Divider */
70 .freq = DT_PROP(OSC_NODE, clock_frequency),
92 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); in clock_init()
119 PMC->REGSC |= PMC_REGSC_BGBE_MASK; in soc_early_init_hook()
/Zephyr-latest/drivers/clock_control/
Dclock_control_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
66 LOG_DBG("RCX calibration done, RCX freq: %d", in calibration_work_cb()
71 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) == in calibration_work_cb()
81 LOG_DBG("RC32K calibration done, RC32K freq: %d", in calibration_work_cb()
108 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) == in xtal32k_settle_work_cb()
118 if ((CRG_TOP->CLK_RC32K_REG & CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk) == 0) { in smartbond_start_rc32k()
119 CRG_TOP->CLK_RC32K_REG |= CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk; in smartbond_start_rc32k()
171 return -ENODEV; in smartbond_clock_set_pll_status()
182 return -EIO; in smartbond_clock_set_pll_status()
224 CRG_TOP->CLK_RC32M_REG |= CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk; in smartbond_clock_control_on()
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Dclock_control_mcux_syscon.c2 * Copyright 2020-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
125 /* 0x1 Clock Select Value Set IRTC to use Osc 32K Clk */ in mcux_lpc_syscon_clock_control_on()
453 * Weak implemenetation of flexspi_clock_set_freq- SOC implementations are
456 __weak int flexspi_clock_set_freq(uint32_t clock_name, uint32_t freq) in flexspi_clock_set_freq() argument
459 ARG_UNUSED(freq); in flexspi_clock_set_freq()
460 return -ENOTSUP; in flexspi_clock_set_freq()
493 ((CLKCTL0->LCDFCLKDIV & CLKCTL0_LCDFCLKDIV_DIV_MASK) + 1)); in mcux_lpc_syscon_clock_control_set_subsys_rate()
500 return -ENOTSUP; in mcux_lpc_syscon_clock_control_set_subsys_rate()
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.c2 * Copyright 2017-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
18 #include <zephyr/dt-bindings/clock/imx_ccm.h>
46 .loopDivider = (DT_PROP(DT_CHILD(CCM_NODE, sys_pll), loop_div) - 20) / 2,
141 * OSC freq in clock_init()
148 /* Set PERIPH_CLK2 MUX to OSC */ in clock_init()
156 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); in clock_init()
159 (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { in clock_init()
180 CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); in clock_init()
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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
49 /* OSC clock */
59 /* OSC clock */
154 /* save usb ip clock freq*/ in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
183 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
203 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()
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/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
89 * and SYSTEM PLL3 by U-Boot. Therefore, there is no need to configure the system PLL again in SOC_ClockInit()
101 /* switch cortex-m7 to SYSTEM PLL1 */ in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
/Zephyr-latest/dts/arm/renesas/ra/
Dra-cm4-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <freq.h>
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
26 xtal: clock-main-osc {
27 compatible = "renesas,ra-cgc-external-clock";
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/Zephyr-latest/dts/arm/nxp/
Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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