Lines Matching +full:osc +full:- +full:freq

2  * Copyright 2022-2023, NXP
4  * SPDX-License-Identifier: Apache-2.0
11  * This module provides routines to initialize and support board-level
49 	/* OSC clock */
59 	/* OSC clock */
154 	/* save usb ip clock freq*/  in usb_device_clock_init()
176 	/*  Wait until host_needclk de-asserts */  in usb_device_clock_init()
177 	while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) {  in usb_device_clock_init()
183 	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;  in usb_device_clock_init()
203 	MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;  in soc_reset_hook()
245 	/* Enable system OSC */  in rt5xx_clock_init()
247 	/* Sets external XTAL OSC freq */  in rt5xx_clock_init()
270 	/* Set up clock selectors - Attach clocks to the peripheries. */  in rt5xx_clock_init()
333 	/* Note- pixel clock follows formula  in rt5xx_clock_init()
352 	/* Enable write-through for FlexSPI1 space */  in rt5xx_clock_init()
353 	CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U;  in rt5xx_clock_init()
354 	CACHE64_POLSEL0->POLSEL = 0x11U;  in rt5xx_clock_init()
423 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK;  in rt5xx_clock_init()
424 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK;  in rt5xx_clock_init()
453 	SYSCTL1->MCLKPINDIR = SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK;  in rt5xx_clock_init()
539 	/* Some ROM versions may have errata leaving these pins in a non-reset state,  in soc_early_init_hook()
543 	IOPCTL->PIO[1][15] = 0;  in soc_early_init_hook()
544 	IOPCTL->PIO[3][28] = 0;  in soc_early_init_hook()
545 	IOPCTL->PIO[3][29] = 0;  in soc_early_init_hook()