1 /*
2 * Copyright (c) 2022 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <assert.h>
8 #include <soc.h>
9 #include <zephyr/sys/onoff.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/clock_control/smartbond_clock_control.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/pm/device.h>
14 #include <da1469x_clock.h>
15 #include <da1469x_qspic.h>
16 #if defined(CONFIG_BT_DA1469X)
17 #include <shm.h>
18 #endif
19 #include <zephyr/drivers/regulator.h>
20
21 LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
22
23 #define DT_DRV_COMPAT smartbond_clock
24
25 struct lpc_clock_state {
26 uint8_t rcx_started : 1;
27 uint8_t rcx_ready : 1;
28 uint8_t rc32k_started : 1;
29 uint8_t rc32k_ready : 1;
30 uint8_t xtal32k_started : 1;
31 uint8_t xtal32k_ready : 1;
32 uint32_t rcx_freq;
33 uint32_t rc32k_freq;
34 } lpc_clock_state = {
35 .rcx_freq = DT_PROP(DT_NODELABEL(rcx), clock_frequency),
36 .rc32k_freq = DT_PROP(DT_NODELABEL(rc32k), clock_frequency),
37 };
38
39 #define CALIBRATION_INTERVAL CONFIG_SMARTBOND_LP_OSC_CALIBRATION_INTERVAL
40
41 #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
42 extern int z_clock_hw_cycles_per_sec;
43 #endif
44
45 static void calibration_work_cb(struct k_work *work);
46 static void xtal32k_settle_work_cb(struct k_work *work);
47 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk);
48
49 static K_WORK_DELAYABLE_DEFINE(calibration_work, calibration_work_cb);
50 static K_WORK_DELAYABLE_DEFINE(xtal32k_settle_work, xtal32k_settle_work_cb);
51
52 /* PLL can be turned on by requesting it explicitly or when USB is attached */
53 /* PLL requested in DT or manually by application */
54 #define PLL_REQUEST_PLL 1
55 /* PLL requested indirectly by USB driver */
56 #define PLL_REQUEST_USB 2
57 /* Keeps information about blocks that requested PLL */
58 static uint8_t pll_requests;
59
calibration_work_cb(struct k_work * work)60 static void calibration_work_cb(struct k_work *work)
61 {
62 if (lpc_clock_state.rcx_started) {
63 da1469x_clock_lp_rcx_calibrate();
64 lpc_clock_state.rcx_ready = true;
65 lpc_clock_state.rcx_freq = da1469x_clock_lp_rcx_freq_get();
66 LOG_DBG("RCX calibration done, RCX freq: %d",
67 (int)lpc_clock_state.rcx_freq);
68
69 #if defined(CONFIG_BT_DA1469X)
70 /* Update CMAC sleep clock with calculated frequency if RCX is set as lp_clk */
71 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) ==
72 (1 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos)) {
73 cmac_request_lp_clock_freq_set(lpc_clock_state.rcx_freq);
74 }
75 #endif
76 }
77 if (lpc_clock_state.rc32k_started) {
78 da1469x_clock_lp_rc32k_calibrate();
79 lpc_clock_state.rc32k_ready = true;
80 lpc_clock_state.rc32k_freq = da1469x_clock_lp_rc32k_freq_get();
81 LOG_DBG("RC32K calibration done, RC32K freq: %d",
82 (int)lpc_clock_state.rc32k_freq);
83 }
84 k_work_schedule(&calibration_work,
85 K_MSEC(1000 * CALIBRATION_INTERVAL));
86 #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
87 switch (smartbond_source_clock(SMARTBOND_CLK_LP_CLK)) {
88 case SMARTBOND_CLK_RCX:
89 z_clock_hw_cycles_per_sec = lpc_clock_state.rcx_freq;
90 break;
91 case SMARTBOND_CLK_RC32K:
92 z_clock_hw_cycles_per_sec = lpc_clock_state.rc32k_freq;
93 break;
94 default:
95 break;
96 }
97 #endif
98 }
99
xtal32k_settle_work_cb(struct k_work * work)100 static void xtal32k_settle_work_cb(struct k_work *work)
101 {
102 if (lpc_clock_state.xtal32k_started && !lpc_clock_state.xtal32k_ready) {
103 LOG_DBG("XTAL32K settled.");
104 lpc_clock_state.xtal32k_ready = true;
105
106 #if defined(CONFIG_BT_DA1469X)
107 /* Update CMAC sleep clock if XTAL32K is set as lp_clk */
108 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) ==
109 (2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos)) {
110 cmac_request_lp_clock_freq_set(32768);
111 }
112 #endif
113 }
114 }
115
smartbond_start_rc32k(void)116 static void smartbond_start_rc32k(void)
117 {
118 if ((CRG_TOP->CLK_RC32K_REG & CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk) == 0) {
119 CRG_TOP->CLK_RC32K_REG |= CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk;
120 }
121 lpc_clock_state.rc32k_started = true;
122 if (!lpc_clock_state.rc32k_ready) {
123 if (!k_work_is_pending(&calibration_work.work)) {
124 k_work_schedule(&calibration_work,
125 K_MSEC(1000 * CALIBRATION_INTERVAL));
126 }
127 }
128 }
129
smartbond_start_rcx(void)130 static void smartbond_start_rcx(void)
131 {
132 if (!lpc_clock_state.rcx_started) {
133 lpc_clock_state.rcx_ready = false;
134 da1469x_clock_lp_rcx_enable();
135 lpc_clock_state.rcx_started = true;
136 }
137 if (!lpc_clock_state.rcx_ready) {
138 if (!k_work_is_pending(&calibration_work.work)) {
139 k_work_schedule(&calibration_work,
140 K_MSEC(1000 * CALIBRATION_INTERVAL));
141 }
142 }
143 }
144
smartbond_start_xtal32k(void)145 static void smartbond_start_xtal32k(void)
146 {
147 if (!lpc_clock_state.xtal32k_started) {
148 lpc_clock_state.xtal32k_ready = false;
149 da1469x_clock_lp_xtal32k_enable();
150 lpc_clock_state.xtal32k_started = true;
151 k_work_schedule(&xtal32k_settle_work,
152 K_MSEC(DT_PROP(DT_NODELABEL(xtal32k),
153 settle_time)));
154 }
155 }
156
157 #ifdef CONFIG_REGULATOR
158 /*
159 * Should be used to control PLL when the regulator driver is available.
160 * If the latter is available, then the VDD level should be changed when
161 * switching to/from PLL. Otherwise, the VDD level is considered to
162 * be fixed @1.2V which should support both XTAL32M and PLL system clocks.
163 */
smartbond_clock_set_pll_status(bool status)164 static int smartbond_clock_set_pll_status(bool status)
165 {
166 const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(vdd));
167 int ret;
168
169 if (!device_is_ready(dev)) {
170 LOG_ERR("Regulator device is not ready");
171 return -ENODEV;
172 }
173
174 if (status) {
175 /* Enabling PLL requires that VDD be raised to 1.2V */
176 if (regulator_set_voltage(dev, 1200000, 1200000) == 0) {
177 da1469x_clock_sys_pll_enable();
178
179 /* QSPIC read pipe delay should be updated when switching to PLL */
180 } else {
181 LOG_ERR("Failed to set VDD_LEVEL to 1.2V");
182 return -EIO;
183 }
184 } else {
185 /* Disable PLL and switch back to XTAL32M */
186 da1469x_clock_sys_pll_disable();
187
188 /* VDD level can now be switched back to 0.9V */
189 ret = regulator_set_voltage(dev, 900000, 900000);
190 if (ret < 0) {
191 LOG_WRN("Failed to set VDD_LEVEL to 0.9V");
192 } else {
193 /*
194 * System clock should be switched to XTAL32M and VDD should be set to 0.9.
195 * The QSPIC read pipe delay should be updated.
196 */
197 da1469x_qspi_set_read_pipe_delay(QSPIC_ID, 2);
198 }
199 }
200
201 return 0;
202 }
203 #endif
204
smartbond_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)205 static inline int smartbond_clock_control_on(const struct device *dev,
206 clock_control_subsys_t sub_system)
207 {
208 enum smartbond_clock clk = (enum smartbond_clock)(sub_system);
209 int ret = 0;
210
211 ARG_UNUSED(dev);
212
213 switch (clk) {
214 case SMARTBOND_CLK_RC32K:
215 smartbond_start_rc32k();
216 break;
217 case SMARTBOND_CLK_RCX:
218 smartbond_start_rcx();
219 break;
220 case SMARTBOND_CLK_XTAL32K:
221 smartbond_start_xtal32k();
222 break;
223 case SMARTBOND_CLK_RC32M:
224 CRG_TOP->CLK_RC32M_REG |= CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;
225 break;
226 case SMARTBOND_CLK_XTAL32M:
227 da1469x_clock_sys_xtal32m_init();
228 da1469x_clock_sys_xtal32m_enable();
229 break;
230 case SMARTBOND_CLK_USB:
231 case SMARTBOND_CLK_PLL96M:
232 pll_requests = 1 << (clk - SMARTBOND_CLK_PLL96M);
233 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) == 0) {
234 if ((CRG_TOP->CLK_CTRL_REG &
235 CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk) == 0) {
236 da1469x_clock_sys_xtal32m_init();
237 da1469x_clock_sys_xtal32m_enable();
238 da1469x_clock_sys_xtal32m_wait_to_settle();
239 }
240 #if CONFIG_REGULATOR
241 ret = smartbond_clock_set_pll_status(true);
242 #else
243 da1469x_clock_sys_pll_enable();
244 #endif
245 if (pll_requests & PLL_REQUEST_USB) {
246 CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
247 }
248 }
249 break;
250 default:
251 return -ENOTSUP;
252 }
253
254 return ret;
255 }
256
smartbond_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)257 static inline int smartbond_clock_control_off(const struct device *dev,
258 clock_control_subsys_t sub_system)
259 {
260 enum smartbond_clock clk = (enum smartbond_clock)(sub_system);
261 int ret = 0;
262
263 ARG_UNUSED(dev);
264
265 switch (clk) {
266 case SMARTBOND_CLK_RC32K:
267 /* RC32K is used by POWERUP and WAKEUP HW FSM */
268 BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(rc32k)),
269 "RC32K is not allowed to be turned off");
270 ret = -EPERM;
271 break;
272 case SMARTBOND_CLK_RCX:
273 if (((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
274 CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) != 1) {
275 CRG_TOP->CLK_RCX_REG &= ~CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk;
276 lpc_clock_state.rcx_ready = false;
277 lpc_clock_state.rcx_started = false;
278 }
279 break;
280 case SMARTBOND_CLK_XTAL32K:
281 if (((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
282 CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) > 1) {
283 CRG_TOP->CLK_XTAL32K_REG &= ~CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;
284 lpc_clock_state.xtal32k_ready = false;
285 lpc_clock_state.xtal32k_started = false;
286 }
287 break;
288 case SMARTBOND_CLK_RC32M:
289 /* Disable rc32m only if not used as system clock */
290 if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) == 0) {
291 da1469x_clock_sys_rc32m_disable();
292 }
293 break;
294 case SMARTBOND_CLK_XTAL32M:
295 da1469x_clock_sys_xtal32m_init();
296 da1469x_clock_sys_xtal32m_enable();
297 break;
298 case SMARTBOND_CLK_USB:
299 /* Switch USB clock to HCLK to allow for resume */
300 CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
301 __fallthrough;
302 case SMARTBOND_CLK_PLL96M:
303 pll_requests &= ~(1 << (clk - SMARTBOND_CLK_PLL96M));
304 if (pll_requests == 0) {
305 /*
306 * PLL must not be disabled as long as a peripheral e.g. LCDC is enabled
307 * and clocked by PLL.
308 */
309 if (!da1469x_clock_check_device_div1_clock()) {
310 #if CONFIG_REGULATOR
311 ret = smartbond_clock_set_pll_status(false);
312 #else
313 da1469x_clock_sys_pll_disable();
314 #endif
315 } else {
316 ret = -EPERM;
317 }
318 }
319 break;
320 default:
321 return -ENOTSUP;
322 }
323
324 return ret;
325 }
326
smartbond_source_clock(enum smartbond_clock clk)327 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk)
328 {
329 static const enum smartbond_clock lp_clk_src[] = {
330 SMARTBOND_CLK_RC32K,
331 SMARTBOND_CLK_RCX,
332 SMARTBOND_CLK_XTAL32K,
333 SMARTBOND_CLK_XTAL32K,
334 };
335 static const enum smartbond_clock sys_clk_src[] = {
336 SMARTBOND_CLK_XTAL32M,
337 SMARTBOND_CLK_RC32M,
338 SMARTBOND_CLK_LP_CLK,
339 SMARTBOND_CLK_PLL96M,
340 };
341
342 if (clk == SMARTBOND_CLK_SYS_CLK) {
343 clk = sys_clk_src[CRG_TOP->CLK_CTRL_REG &
344 CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk];
345 }
346 /* System clock can be low power clock, so next check is not in else */
347 if (clk == SMARTBOND_CLK_LP_CLK) {
348 clk = lp_clk_src[(CRG_TOP->CLK_CTRL_REG &
349 CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
350 CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos];
351 }
352 return clk;
353 }
354
smartbond_clock_get_rate(enum smartbond_clock clk,uint32_t * rate)355 static int smartbond_clock_get_rate(enum smartbond_clock clk, uint32_t *rate)
356 {
357 clk = smartbond_source_clock(clk);
358 switch (clk) {
359 case SMARTBOND_CLK_RC32K:
360 *rate = lpc_clock_state.rc32k_freq;
361 break;
362 case SMARTBOND_CLK_RCX:
363 *rate = lpc_clock_state.rcx_freq;
364 break;
365 case SMARTBOND_CLK_XTAL32K:
366 *rate = DT_PROP(DT_NODELABEL(xtal32k), clock_frequency);
367 break;
368 case SMARTBOND_CLK_RC32M:
369 *rate = DT_PROP(DT_NODELABEL(rc32m), clock_frequency);
370 break;
371 case SMARTBOND_CLK_XTAL32M:
372 *rate = DT_PROP(DT_NODELABEL(xtal32m), clock_frequency);
373 break;
374 case SMARTBOND_CLK_PLL96M:
375 *rate = DT_PROP(DT_NODELABEL(pll), clock_frequency);
376 break;
377 case SMARTBOND_CLK_USB:
378 *rate = 48000000;
379 break;
380 default:
381 return -ENOTSUP;
382 }
383 return 0;
384 }
385
smartbond_clock_control_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)386 static int smartbond_clock_control_get_rate(const struct device *dev,
387 clock_control_subsys_t sub_system,
388 uint32_t *rate)
389 {
390 ARG_UNUSED(dev);
391
392 return smartbond_clock_get_rate((enum smartbond_clock)(sub_system), rate);
393 }
394
smartbond_dt_ord_to_clock(uint32_t dt_ord)395 static enum smartbond_clock smartbond_dt_ord_to_clock(uint32_t dt_ord)
396 {
397 switch (dt_ord) {
398 case DT_DEP_ORD(DT_NODELABEL(rc32k)):
399 return SMARTBOND_CLK_RC32K;
400 case DT_DEP_ORD(DT_NODELABEL(rcx)):
401 return SMARTBOND_CLK_RCX;
402 case DT_DEP_ORD(DT_NODELABEL(xtal32k)):
403 return SMARTBOND_CLK_XTAL32K;
404 case DT_DEP_ORD(DT_NODELABEL(rc32m)):
405 return SMARTBOND_CLK_RC32M;
406 case DT_DEP_ORD(DT_NODELABEL(xtal32m)):
407 return SMARTBOND_CLK_XTAL32M;
408 case DT_DEP_ORD(DT_NODELABEL(pll)):
409 return SMARTBOND_CLK_PLL96M;
410 default:
411 return SMARTBOND_CLK_NONE;
412 }
413 }
414
smartbond_clock_control_on_by_ord(const struct device * dev,uint32_t clock_id)415 static void smartbond_clock_control_on_by_ord(const struct device *dev,
416 uint32_t clock_id)
417 {
418 enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id);
419
420 smartbond_clock_control_on(dev, (clock_control_subsys_rate_t)clk);
421 }
422
smartbond_clock_control_off_by_ord(const struct device * dev,uint32_t clock_id)423 static void smartbond_clock_control_off_by_ord(const struct device *dev,
424 uint32_t clock_id)
425 {
426 enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id);
427
428 smartbond_clock_control_off(dev, (clock_control_subsys_rate_t)clk);
429 }
430
z_smartbond_select_lp_clk(enum smartbond_clock lp_clk)431 int z_smartbond_select_lp_clk(enum smartbond_clock lp_clk)
432 {
433 int rc = 0;
434 uint32_t clk_sel = 0;
435 uint32_t clk_sel_msk = CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk;
436
437 switch (lp_clk) {
438 case SMARTBOND_CLK_RC32K:
439 clk_sel = 0;
440 break;
441 case SMARTBOND_CLK_RCX:
442 clk_sel = 1 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos;
443 break;
444 case SMARTBOND_CLK_XTAL32K:
445 clk_sel = 2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos;
446 break;
447 default:
448 rc = -EINVAL;
449 }
450
451 if (rc == 0) {
452 #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
453 switch (lp_clk) {
454 case SMARTBOND_CLK_RCX:
455 z_clock_hw_cycles_per_sec = lpc_clock_state.rcx_freq;
456 break;
457 case SMARTBOND_CLK_RC32K:
458 z_clock_hw_cycles_per_sec = lpc_clock_state.rc32k_freq;
459 break;
460 default:
461 z_clock_hw_cycles_per_sec = 32768;
462 break;
463 }
464 #endif
465 CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG & ~clk_sel_msk) | clk_sel;
466 }
467
468 return rc;
469 }
470
smartbond_clock_control_update_memory_settings(uint32_t sys_clock_freq)471 static void smartbond_clock_control_update_memory_settings(uint32_t sys_clock_freq)
472 {
473 if (sys_clock_freq > 32000000) {
474 da1469x_qspi_set_read_pipe_delay(QSPIC_ID, 7);
475 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
476 da1469x_qspi_set_read_pipe_delay(QSPIC2_ID, 7);
477 #endif
478 } else {
479 da1469x_qspi_set_read_pipe_delay(QSPIC_ID, 2);
480 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
481 da1469x_qspi_set_read_pipe_delay(QSPIC2_ID, 2);
482 #endif
483 }
484
485 da1469x_qspi_set_cs_delay(QSPIC_ID, SystemCoreClock,
486 DT_PROP(DT_NODELABEL(flash_controller), read_cs_idle_delay),
487 DT_PROP(DT_NODELABEL(flash_controller), erase_cs_idle_delay));
488 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
489 da1469x_qspi_set_cs_delay(QSPIC2_ID, SystemCoreClock,
490 DT_PROP(DT_NODELABEL(memc), read_cs_idle_min_ns),
491 DT_PROP_OR(DT_NODELABEL(memc), erase_cs_idle_min_ns, 0));
492 #if DT_PROP(DT_NODELABEL(memc), is_ram)
493 da1469x_qspi_set_tcem(SystemCoreClock, DT_PROP(DT_NODELABEL(memc), tcem_max_us));
494 #endif
495 #endif
496 }
497
z_smartbond_select_sys_clk(enum smartbond_clock sys_clk)498 int z_smartbond_select_sys_clk(enum smartbond_clock sys_clk)
499 {
500 uint32_t sys_clock_freq;
501 uint32_t clk_sel;
502 uint32_t clk_sel_msk = CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
503 int res = 0;
504
505 res = smartbond_clock_get_rate(sys_clk, &sys_clock_freq);
506 if (res != 0) {
507 return -EINVAL;
508 }
509
510 /* When PLL is selected as system clock qspi read pipe delay must be set to 7 */
511 if (sys_clock_freq > 32000000) {
512 smartbond_clock_control_update_memory_settings(sys_clock_freq);
513 }
514
515 if (sys_clk == SMARTBOND_CLK_RC32M) {
516 clk_sel = 1 << CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos;
517 CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG & ~clk_sel_msk) | clk_sel;
518 SystemCoreClock = sys_clock_freq;
519 } else if (sys_clk == SMARTBOND_CLK_PLL96M) {
520 /* Check that PLL is already enabled, otherwise enable it. */
521 if (!da1469x_clock_sys_pll_is_enabled()) {
522 #if CONFIG_REGULATOR
523 res = smartbond_clock_set_pll_status(true);
524 if (res != 0) {
525 return -EIO;
526 }
527 #else
528 da1469x_clock_sys_pll_enable();
529 #endif
530 }
531 da1469x_clock_sys_pll_switch();
532 } else if (sys_clk == SMARTBOND_CLK_XTAL32M) {
533 /*
534 * XTAL32M should be enabled eitherway as it's not allowed
535 * to be turned off by application.
536 */
537 da1469x_clock_sys_xtal32m_switch_safe();
538 } else {
539 return -EINVAL;
540 }
541
542 /* When switching back from PLL to 32MHz read pipe delay may be set to 2 */
543 if (SystemCoreClock <= 32000000) {
544 smartbond_clock_control_update_memory_settings(SystemCoreClock);
545 }
546
547 return res;
548 }
549
550 /**
551 * @brief Initialize clocks for the Smartbond
552 *
553 * This routine is called to enable and configure the clocks and PLL
554 * of the soc on the board.
555 *
556 * @param dev clocks device struct
557 *
558 * @return 0
559 */
smartbond_clocks_init(const struct device * dev)560 int smartbond_clocks_init(const struct device *dev)
561 {
562 uint32_t clk_id;
563 enum smartbond_clock lp_clk;
564 enum smartbond_clock sys_clk;
565
566 ARG_UNUSED(dev);
567
568 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
569 /* Make sure QSPIC2 is enabled */
570 da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk);
571 #endif
572
573 #define ENABLE_OSC(clock) smartbond_clock_control_on_by_ord(dev, DT_DEP_ORD(clock))
574 #define DISABLE_OSC(clock) if (DT_NODE_HAS_STATUS(clock, disabled)) { \
575 smartbond_clock_control_off_by_ord(dev, DT_DEP_ORD(clock)); \
576 }
577
578 /* Enable all oscillators with status "okay" */
579 DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(crg, osc), ENABLE_OSC, (;));
580
581 /* Make sure that selected sysclock is enabled */
582 BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(DT_PROP(DT_NODELABEL(sys_clk), clock_src)),
583 "Clock selected as system clock no enabled in DT");
584 BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(DT_PROP(DT_NODELABEL(lp_clk), clock_src)),
585 "Clock selected as LP clock no enabled in DT");
586 BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(pll), disabled) ||
587 DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(xtal32m)),
588 "PLL enabled in DT but XTAL32M is disabled");
589
590 clk_id = DT_DEP_ORD(DT_PROP(DT_NODELABEL(lp_clk), clock_src));
591 lp_clk = smartbond_dt_ord_to_clock(clk_id);
592 z_smartbond_select_lp_clk(lp_clk);
593
594 clk_id = DT_DEP_ORD(DT_PROP(DT_NODELABEL(sys_clk), clock_src));
595 sys_clk = smartbond_dt_ord_to_clock(clk_id);
596 smartbond_clock_control_on(dev,
597 (clock_control_subsys_rate_t)smartbond_source_clock(sys_clk));
598 z_smartbond_select_sys_clk(sys_clk);
599
600 /* Disable unwanted oscillators */
601 DT_FOREACH_CHILD_SEP(DT_PATH(crg, osc), DISABLE_OSC, (;));
602
603 return 0;
604 }
605
606 static DEVICE_API(clock_control, smartbond_clock_control_api) = {
607 .on = smartbond_clock_control_on,
608 .off = smartbond_clock_control_off,
609 .get_rate = smartbond_clock_control_get_rate,
610 };
611
612 #if CONFIG_PM_DEVICE
smartbond_clocks_pm_action(const struct device * dev,enum pm_device_action action)613 static int smartbond_clocks_pm_action(const struct device *dev, enum pm_device_action action)
614 {
615 switch (action) {
616 case PM_DEVICE_ACTION_SUSPEND:
617 break;
618 case PM_DEVICE_ACTION_RESUME:
619 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
620 /* Make sure QSPIC2 is enabled */
621 da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk);
622 #endif
623 /*
624 * Make sure the flash controller has correct settings as clock restoration
625 * might have been performed upon waking up.
626 */
627 smartbond_clock_control_update_memory_settings(SystemCoreClock);
628 break;
629 default:
630 return -ENOTSUP;
631 }
632
633 return 0;
634 }
635 #endif
636
637 PM_DEVICE_DT_DEFINE(DT_NODELABEL(osc), smartbond_clocks_pm_action);
638
639 DEVICE_DT_DEFINE(DT_NODELABEL(osc),
640 smartbond_clocks_init,
641 PM_DEVICE_DT_GET(DT_NODELABEL(osc)),
642 NULL, NULL,
643 PRE_KERNEL_1,
644 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
645 &smartbond_clock_control_api);
646
