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/Zephyr-latest/dts/bindings/pinctrl/
Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
[all …]
/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc_config.c3 * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
25 /* Disable ERASE function on PB12 pin, this is controlled in atmel_samv71_config()
28 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; in atmel_samv71_config()
31 /* In Cortex-M based SoCs JTAG interface can be used to perform in atmel_samv71_config()
32 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug in atmel_samv71_config()
33 * interface therefore there is no harm done by disabling the JTAG TDI in atmel_samv71_config()
36 /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix in atmel_samv71_config()
38 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; in atmel_samv71_config()
41 /* Disable PCK3 clock used by ETM module */ in atmel_samv71_config()
[all …]
Dsoc.c3 * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
40 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
99 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
111 * CPU using JTAG. in soc_reset_hook()
117 * DTCM is enabled by default at reset, therefore we have to disable in soc_reset_hook()
119 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
144 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
[all …]
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc_config.c4 * SPDX-License-Identifier: Apache-2.0
25 /* Disable ERASE function on PB12 pin, this is controlled in atmel_same70_config()
28 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; in atmel_same70_config()
31 /* In Cortex-M based SoCs JTAG interface can be used to perform in atmel_same70_config()
32 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug in atmel_same70_config()
33 * interface therefore there is no harm done by disabling the JTAG TDI in atmel_same70_config()
36 /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ in atmel_same70_config()
37 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; in atmel_same70_config()
40 /* Disable PCK3 clock used by ETM module */ in atmel_same70_config()
41 PMC->PMC_SCDR = PMC_SCDR_PCK3; in atmel_same70_config()
[all …]
Dsoc.c3 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
42 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
70 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
102 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
114 * CPU using JTAG. in soc_reset_hook()
120 * DTCM is enabled by default at reset, therefore we have to disable in soc_reset_hook()
122 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
147 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
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/Zephyr-latest/drivers/serial/
DKconfig.altera_jtag1 # Copyright (c) 2017-2023 Intel Corporation
2 # SPDX-License-Identifier: Apache-2.0
5 bool "Nios II/NiosV JTAG UART driver"
10 Enable the Altera JTAG UART driver, built in to many Nios II/NiosV CPU
14 bool "JTAG UART driver using Altera HAL API"
18 Enabling this will disable poll_in and interrupt driven api.
26 This is a helper config. Altera JTAG UART driver will support interrupt,
/Zephyr-latest/soc/microchip/mec/mec172x/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
29 bool "Disable debug support"
31 Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
32 pin is ignored. All other JTAG pins can be used as GPIOs
33 or other non-JTAG alternate functions.
38 JTAG port in SWD mode. I2C09 and ADC00-03 can be used.
43 JTAG port is enabled in SWD mode. Refer to tracing options
44 to see if ADC00-03 can be used or not.
57 JTAG port in SWD mode and ETM as tracing method.
58 I2C09 can be used, but ADC00-03 cannot.
[all …]
Ddevice_power.h4 * SPDX-License-Identifier: Apache-2.0
16 * Disable UART deep sleep save/restore. If a UART TX FIFO has data on deep
17 * sleep entry it will de-assert its CLK_REQ once TX FIFO empties. If the
22 /* Comment out to use JTAG without interruptions.
25 * Note: To attach JTAG for any debug need to be performed with breakpoint
40 * peripherals, disable them, and restore the enabled state upon
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
34 * We touch the Cortex-M's primary mask and base priority registers
41 * If a JTAG/SWD debug probe is connected driving TRST# high and
43 * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
44 * while a probe is using the interface. This can leave the JTAG/SWD
72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
73 pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY; in z_power_soc_deep_sleep()
74 pcr->OSC_ID = pcr->SYS_SLP_CTRL; in z_power_soc_deep_sleep()
86 * PM post ops. This de-asserts peripheral SLP_EN signals. in z_power_soc_deep_sleep()
88 pcr->SYS_SLP_CTRL = 0U; in z_power_soc_deep_sleep()
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
53 bool "Disable debug support"
55 Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
56 pin is ignored. All other JTAG pins can be used as GPIOs
57 or other non-JTAG alternate functions.
62 JTAG port in SWD mode. UART2 and ADC00-03 can be used.
67 JTAG port is enabled in SWD mode. Refer to tracing options
68 to see if ADC00-03 can be used or not.
82 JTAG port in SWD mode and SWV as tracing method.
83 UART2 can be used, but ADC00-03 cannot.
[all …]
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
26 * We touch the Cortex-M's primary mask and base priority registers
33 * If a JTAG/SWD debug probe is connected driving TRST# high and
35 * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
36 * while a probe is using the interface. This can leave the JTAG/SWD
67 while ((PCR_REGS->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) { in z_power_soc_deep_sleep()
123 * arch_irq_lock() which sets BASEPRI to a non-zero value masking all interrupts
126 * an ISR on wake except for faults. We re-enable interrupts by setting PRIMASK
/Zephyr-latest/boards/silabs/dev_kits/sim3u1xx_dk/support/
Dopenocd.cfg3 # SPDX-License-Identifier: Apache-2.0
5 source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg]
6 source [find interface/ftdi/olimex-arm-jtag-swd.cfg]
10 # On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the
12 # chip's errata: https://www.silabs.com/documents/public/errata/SiM3U1xx-SiM3C1xxErrata.pdf
15 $_TARGETNAME configure -event gdb-attach {
21 $_TARGETNAME configure -event gdb-detach {
/Zephyr-latest/boards/gardena/sgrm/support/
Dopenocd.cfg3 # SPDX-License-Identifier: Apache-2.0
5 source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg]
6 source [find interface/ftdi/olimex-arm-jtag-swd.cfg]
10 # On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the
12 # chip's errata: https://www.silabs.com/documents/public/errata/SiM3U1xx-SiM3C1xxErrata.pdf
15 $_TARGETNAME configure -event gdb-attach {
21 $_TARGETNAME configure -event gdb-detach {
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 bool "SPI flash operates full-duplex with fast reading mode"
223 bool "Disable debug support"
225 Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
226 pin is ignored. All other JTAG pins can be used as GPIOs
227 or other non-JTAG alternate functions.
232 JTAG port in SWD mode.
[all …]
/Zephyr-latest/boards/nxp/s32z2xxdc2/support/
Dstartup.cmm3 ; SPDX-License-Identifier: Apache-2.0 *
5 ; Lauterbach Trace32 start-up script for S32Z27x / Cortex-R52 *
8 ; - command operation to execute *
11 ; - elfFile filepath of ELF to load *
12 ; - rtu Real-Time Unit (RTU) index *
15 ; - core core index, relative to the RTU *
18 ; - lockstep set to "yes" to start the core in lock-step mode *
20 ; - Core0 and Core2 (redundancy) operate as a lockstep pair *
21 ; - Core1 and Core3 (redundancy) operate as a lockstep pair *
59 ; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
19 * ITE EC chip from dtsi (include status disable). Both it81202 and
34 /* PLL Frequency Auto-Calibration Control 0 Register */
44 /* PLL Frequency Auto-Calibration Control 2 Register */
79 return -ERANGE; in chip_get_pll_freq()
129 * JTAG div = 1 (PLL / 2 = 24 mhz)
157 * JTAG div = 3 (PLL / 4 = 24 mhz)
191 IT8XXX2_ECPM_PLLFREQR = pll->pll_freq; in chip_run_pll_sequence()
192 /* Pre-set FND clock frequency = PLL / 3 */ in chip_run_pll_sequence()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecs.h4 * SPDX-License-Identifier: Apache-2.0
54 /* PECI Disable */
66 /* Boot-ROM Status */
74 /* JTAG Controller Config */
89 /* JTAG Controller Status */
98 /* JTAG Controller Command */
178 uint32_t RSVD8[(0xb0 - 0x9c) / 4];
183 uint32_t RSVD9[(0x144 - 0xc0) / 4];
/Zephyr-latest/soc/atmel/sam/sam4e/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
5 * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
8 * SPDX-License-Identifier: Apache-2.0
15 * This module provides routines to initialize and support board-level hardware
39 EFC->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
86 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
98 * CPU using JTAG. in soc_reset_hook()
/Zephyr-latest/soc/atmel/sam/common/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
15 crystal needs to stabilize after power-up.
29 crystal needs to stabilize after power-up.
84 For JTAG debugging CPU clock (HCLK) should not stop. In order to
89 bool "Disable ERASE pin"
/Zephyr-latest/soc/atmel/sam/sam3x/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
5 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
7 * SPDX-License-Identifier: Apache-2.0
14 * This module provides routines to initialize and support board-level hardware
36 EFC0->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
37 EFC1->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
64 EFC0->EEFC_FMR = EEFC_FMR_FWS(4); in clock_init()
65 EFC1->EEFC_FMR = EEFC_FMR_FWS(4); in clock_init()
94 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
106 * CPU using JTAG. in soc_reset_hook()
/Zephyr-latest/soc/atmel/sam/sam4s/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
6 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
8 * SPDX-License-Identifier: Apache-2.0
15 * This module provides routines to initialize and support board-level hardware
39 EFC0->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
41 EFC1->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
71 EFC0->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
73 EFC1->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
92 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
104 * CPU using JTAG. in soc_reset_hook()
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
Dsoc.c3 * SPDX-License-Identifier: Apache-2.0
64 /* Platform-specific early initialization */
69 * When coming out of u-boot rather than downloading the Zephyr binary in soc_reset_hook()
70 * via JTAG, a few things modified by u-boot have to be re-set to a in soc_reset_hook()
73 * - u-boot places the exception vectors somewhere in RAM and then in soc_reset_hook()
79 * - u-boot sets the following bits in the SCTLR register: in soc_reset_hook()
80 * - [I] ICache enable in soc_reset_hook()
81 * - [C] DCache enable in soc_reset_hook()
82 * - [Z] Branch prediction enable in soc_reset_hook()
83 * - [A] Enforce strict alignment enable in soc_reset_hook()
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
Dsoc.c3 * SPDX-License-Identifier: Apache-2.0
64 /* Platform-specific early initialization */
69 * When coming out of u-boot rather than downloading the Zephyr binary in soc_reset_hook()
70 * via JTAG, a few things modified by u-boot have to be re-set to a in soc_reset_hook()
73 * - u-boot places the exception vectors somewhere in RAM and then in soc_reset_hook()
79 * - u-boot sets the following bits in the SCTLR register: in soc_reset_hook()
80 * - [I] ICache enable in soc_reset_hook()
81 * - [C] DCache enable in soc_reset_hook()
82 * - [Z] Branch prediction enable in soc_reset_hook()
83 * - [A] Enforce strict alignment enable in soc_reset_hook()
[all …]
/Zephyr-latest/boards/nxp/mr_canhubk3/support/
Dstartup.cmm4 ; Lauterbach Trace32 start-up script for S32K344 / Cortex-M7 *
7 ; - command operation to execute *
9 ; - elfFile filepath of ELF to load *
10 ; - loadTo if "flash", the application will be downloaded to SoC *
15 ; - eraseFlash if set to "yes", the whole content in Flash device will be *
19 ; - verifyFlash if set to "yes", verify after program application to Flash *
42 SYStem.CPU S32K344-M7
43 SYStem.CONFIG.DEBUGPORTTYPE JTAG
48 Trace.DISable
62 FLASH.CHANGEtype 0x007D4000--0x7F3FFF TARGET
[all …]
/Zephyr-latest/boards/phytec/phyboard_pollux/doc/
Dindex.rst3 phyBOARD-Pollux i.MX8M Plus
9 The phyBOARD-Pollux is based upon the phyCORE-i.MX8M Plus SOM which is based on
10 the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one
11 Coretex-M7 core for real time applications like Zephyr. The phyBOARD-Pollux
19 - Memory:
21 - RAM: 256MB - 8GB LPDDR4
22 - EEPROM: 4kB - 32kB
23 - eMMC: 4GB - 64GB (eMMC 5.1)
24 - SPI NOR Flash: 4MB - 256MB
25 - Interfaces:
[all …]

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