1 /*
2  * Copyright (c) 2013-2015 Wind River Systems, Inc.
3  * Copyright (c) 2016 Intel Corporation.
4  * Copyright (c) 2017 Justin Watson
5  * Copyright (c) 2023 Basalte bv
6  * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
7  *
8  * SPDX-License-Identifier: Apache-2.0
9  */
10 
11 /**
12  * @file
13  * @brief Atmel SAM4S MCU series initialization code
14  *
15  * This module provides routines to initialize and support board-level hardware
16  * for the Atmel SAM4S series processor.
17  */
18 
19 #include <soc.h>
20 #include <soc_pmc.h>
21 #include <soc_supc.h>
22 
23 /**
24  * @brief Setup various clock on SoC at boot time.
25  *
26  * Setup the SoC clocks according to section 28.12 in datasheet.
27  *
28  * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
29  * It is assumed that the relevant registers are at their reset value.
30  */
clock_init(void)31 static ALWAYS_INLINE void clock_init(void)
32 {
33 	/* Switch the main clock to the internal OSC with 12MHz */
34 	soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
35 
36 	/* Switch MCK (Master Clock) to the main clock */
37 	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
38 
39 	EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
40 #if defined(ID_EFC1)
41 	EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
42 #endif
43 
44 	soc_pmc_enable_clock_failure_detector();
45 
46 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
47 		soc_supc_slow_clock_select_crystal_osc();
48 	}
49 
50 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
51 		/*
52 		 * Setup main external crystal oscillator.
53 		 */
54 
55 		/* We select maximum setup time.
56 		 * While start up time could be shortened
57 		 * this optimization is not deemed
58 		 * critical now.
59 		 */
60 		soc_pmc_switch_mainck_to_xtal(false, 0xff);
61 	}
62 
63 	/*
64 	 * Set FWS (Flash Wait State) value before increasing Master Clock
65 	 * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet.
66 	 * This is set to the highest number of read cycles because it won't
67 	 * hurt lower clock frequencies. However, a high frequency with too
68 	 * few read cycles could cause flash read problems. FWS 5 (6 cycles)
69 	 * is the safe setting for all of this SoCs usable frequencies.
70 	 */
71 	EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
72 #if defined(ID_EFC1)
73 	EFC1->EEFC_FMR = EEFC_FMR_FWS(5);
74 #endif
75 
76 	/*
77 	 * Setup PLLA
78 	 */
79 	soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
80 			      CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
81 
82 	/*
83 	 * Final setup of the Master Clock
84 	 */
85 
86 	/* prescaler has to be set before PLL lock */
87 	soc_pmc_mck_set_prescaler(1);
88 
89 	/* Select PLL as Master Clock source. */
90 	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
91 
92 	/* Disable internal fast RC if we have an external crystal oscillator */
93 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
94 		soc_pmc_osc_disable_fastrc();
95 	}
96 }
97 
soc_reset_hook(void)98 void soc_reset_hook(void)
99 {
100 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
101 		/*
102 		 * Instruct CPU to enter Wait mode instead of Sleep mode to
103 		 * keep Processor Clock (HCLK) and thus be able to debug
104 		 * CPU using JTAG.
105 		 */
106 		soc_pmc_enable_waitmode();
107 	}
108 
109 	/* Setup system clocks. */
110 	clock_init();
111 }
112