1;*******************************************************************************
2;   Copyright 2022 NXP                                                         *
3;   SPDX-License-Identifier: Apache-2.0                                        *
4;                                                                              *
5;   Lauterbach Trace32 start-up script for S32Z27x / Cortex-R52                *
6;                                                                              *
7;   Parameters:                                                                *
8;   - command     operation to execute                                         *
9;                 valid values: flash, debug                                   *
10;                 default: debug                                               *
11;   - elfFile     filepath of ELF to load                                      *
12;   - rtu         Real-Time Unit (RTU) index                                   *
13;                 valid values: 0, 1                                           *
14;                 default: 0                                                   *
15;   - core        core index, relative to the RTU                              *
16;                 valid values: 0 to 3                                         *
17;                 default: 0                                                   *
18;   - lockstep    set to "yes" to start the core in lock-step mode             *
19;                 in Lockstep mode:                                            *
20;                  - Core0 and Core2 (redundancy) operate as a lockstep pair   *
21;                  - Core1 and Core3 (redundancy) operate as a lockstep pair   *
22;                 default: yes                                                 *
23;                                                                              *
24;*******************************************************************************
25
26ENTRY %LINE &args
27LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit
28
29&command=STRing.SCANAndExtract("&args","command=","debug")
30&elfFile=STRing.SCANAndExtract("&args","elfFile=","")
31&rtu=STRing.SCANAndExtract("&args","rtu=","0")
32&core=STRing.SCANAndExtract("&args","core=","0")
33&lockstep=STRing.SCANAndExtract("&args","lockstep=","yes")
34
35IF ("&elfFile"=="")
36(
37  PRINT %ERROR "Missing ELF file path"
38  PLIST
39  STOP
40  ENDDO
41)
42
43IF (&rtu<0||&rtu>1)
44(
45  PRINT %ERROR "Invalid rtu number: &rtu"
46  PLIST
47  STOP
48  ENDDO
49)
50
51IF (&core<0||&core>3)
52(
53  PRINT %ERROR "Invalid core number: &core"
54  PLIST
55  STOP
56  ENDDO
57)
58
59; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit)
60IF ("&lockstep"=="yes")
61  &spltLckBit="0"
62ELSE
63  &spltLckBit="1"
64
65IF ("&rtu"=="0")
66(
67  &rtuStartAddr = 0x79900000
68  &cfgCoreAddr = 0x76120000
69)
70ELSE
71(
72  &rtuStartAddr = 0x7D900000
73  &cfgCoreAddr = 0x76920000
74)
75
76; Trace32 indexes are offset by 1
77&coreId=&core+1
78&rtuId=&rtu+1
79
80; Reset
81ON.ERROR.CONTinue
82JTAG.PIN NRESET 0
83JTAG.PIN NTRST 0
84WAIT 10ms
85JTAG.PIN NRESET 1
86JTAG.PIN NTRST 1
87WAIT 10ms
88ON.ERROR.DEFault
89
90; Initialize debugger
91SYStem.Down
92SYStem.CPU S32Z270-M33-SMU
93SYStem.CONFIG.DEBUGPORTTYPE JTAG
94SYStem.Option.DUALPORT ON
95SYStem.MemAccess DAP
96SYStem.JtagClock 40MHz
97Trace.DISable
98ETM.OFF
99ITM.OFF
100
101SYStem.Mode Prepare
102WAIT 1.s
103
104; Disable Functional Reset Escalation Threshold
105Data.Set EAXI:0x41850014 %LE %Long 0x0
106Data.Set EAXI:0x41850018 %LE %Long 0x0
107Data.Set EAXI:0x4185001C %LE %Long 0x0
108
109; Configure Miscellaneous Debug Module AP (MDM-AP) for RTU's
110Data.Set DP:0x1C100c0 %LE %Long 0x3cf3cf00
111Data.Set DP:0x1C100c8 %LE %Long 0x3cf3cf00
112
113; RTU subsystems out of reset logic
114GOSUB EnableRTU0
115GOSUB EnableRTU1
116
117; Init RTU SRAM
118DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm
119
120; Set reset value for split-lock mode
121Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit)  ; CFG_CORE
122
123; Write loop to self instruction
124Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF
125
126; Wake up core
127GOSUB EnableR52_&(rtu)_&(core)
128
129; Reconfigure debugger
130SYStem.CPU S32Z270-R52-RTU&(rtu)
131CORE.ASSIGN &coreId
132SYStem.CONFIG.CORE &coreId &rtuId
133SYStem.Option.DUALPORT ON
134SYStem.Option.ResBreak OFF
135SYStem.Option.EnReset  OFF
136Trace.DISable
137ETM.OFF
138STM.OFF
139
140WAIT 200ms
141SYStem.Attach
142
143IF STATE.RUN()
144  Break
145
146; Load application to SRAM, running from flash is not yet supported
147Data.LOAD.Elf &elfFile EAXI:
148
149SYStem.MemAccess.AXI
150
151SYStem.CONFIG.AHBAP1.Base DP:0x1C80000
152SYStem.CONFIG.APBAP1.Base DP:0x1C30000
153SYStem.CONFIG.AXIAP1.Base DP:0x1C21000
154
155Register.Set PC __start
156
157IF ("&command"=="flash")
158(
159  ; Execute the application and quit
160  Go
161  QUIT
162)
163ELSE
164(
165  ; Setup minimal debug environment
166  WinCLEAR
167  SETUP.Var.%SpotLight
168  WinPOS 0. 0. 120. 30.
169  List.auto
170  WinPOS 125. 0. 80. 10.
171  Frame.view
172  WinPOS 125. 18.
173  Register.view /SpotLight
174)
175
176ENDDO
177
178EnableRTU0:
179(
180  ; RTU0 subsystem out of reset logic (MC_ME)
181  Data.Set EAXI:0x41900300 %LE %Long 0x5
182  Data.Set EAXI:0x41900304 %LE %Long 0x1
183  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
184  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
185  WAIT 100ms
186
187  ; Deactivate RTU fencing logic (GPR3)
188  Data.Set EAXI:0x4186005c %LE %Long 0x0
189
190  ; Enable the interconnect interface of reset domain
191  Data.Set EAXI:0x41890004 %LE %Long 0x80000000
192  Data.Set EAXI:0x41890004 %LE %Long 0x80000007
193
194  ; Assert reset (RGM)
195  Data.Set EAXI:0x41850048 %LE %Long 0x1E
196
197  ; Clear OSSE bit and set clock update (MC_ME)
198  Data.Set EAXI:0x41900300 %LE %Long 0x1
199  Data.Set EAXI:0x41900304 %LE %Long 0x4
200  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
201  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
202  WAIT 200ms
203
204  RETURN
205)
206
207EnableRTU1:
208(
209  ; RTU1 subsystem out of reset logic (MC_ME)
210  Data.Set EAXI:0x41900500 %LE %Long 0x5
211  Data.Set EAXI:0x41900504 %LE %Long 0x1
212  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
213  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
214  WAIT 100ms
215
216  ; Deactivate RTU fencing logic (GPR3)
217  Data.Set EAXI:0x41860064 %LE %Long 0x0
218
219  ; Enable the interconnect interface of reset domain
220  Data.Set EAXI:0x418A0004 %LE %Long 0x80000000
221  Data.Set EAXI:0x418A0004 %LE %Long 0x80000007
222
223  ; Assert reset (RGM)
224  Data.Set EAXI:0x41850050 %LE %Long 0x1E
225
226  ; Clear OSSE bit and set clock update (MC_ME)
227  Data.Set EAXI:0x41900500 %LE %Long 0x1
228  Data.Set EAXI:0x41900504 %LE %Long 0x4
229  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
230  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
231  WAIT 200ms
232
233  ; Enable RTU1 NIC
234  Data.Set EAXI:0x75400000 %LE %Long 0x2    ; RTUM_NIC
235  Data.Set EAXI:0x75500000 %LE %Long 0x2    ; RTUF_NIC
236  Data.Set EAXI:0x75600000 %LE %Long 0x2    ; RTUP_NIC
237  Data.Set EAXI:0x75700000 %LE %Long 0x2    ; RTUE_NIC
238
239  RETURN
240)
241
242; EnableR52_<core>_<rtu> - routines for waking up the RTU cores:
243; - set boot address (MC_ME_PRTNy_COREx_ADDR)
244; - enable core clock
245; - trigger the clock update
246; - store key for starting the hw process
247; - force core reset
248
249EnableR52_0_0:
250(
251  Data.Set EAXI:0x4190034C %LE %Long &rtuStartAddr
252  Data.Set EAXI:0x41900340 %LE %Long 0x1
253  Data.Set EAXI:0x41900344 %LE %Long 0x1
254  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
255  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
256  Data.Set EAXI:0x41850048 %LE %Long 0x1C
257  RETURN
258)
259
260EnableR52_0_1:
261(
262  Data.Set EAXI:0x4190036C %LE %Long &rtuStartAddr
263  Data.Set EAXI:0x41900360 %LE %Long 0x1
264  Data.Set EAXI:0x41900364 %LE %Long 0x1
265  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
266  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
267  Data.Set EAXI:0x41850048 %LE %Long 0x18
268  RETURN
269)
270
271EnableR52_0_2:
272(
273  Data.Set EAXI:0x4190038C %LE %Long &rtuStartAddr
274  Data.Set EAXI:0x41900380 %LE %Long 0x1
275  Data.Set EAXI:0x41900384 %LE %Long 0x1
276  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
277  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
278  Data.Set EAXI:0x41850048 %LE %Long 0x10
279  RETURN
280)
281
282EnableR52_0_3:
283(
284  Data.Set EAXI:0x419003AC %LE %Long &rtuStartAddr
285  Data.Set EAXI:0x419003A0 %LE %Long 0x1
286  Data.Set EAXI:0x419003A4 %LE %Long 0x1
287  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
288  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
289  Data.Set EAXI:0x41850048 %LE %Long 0x0
290  RETURN
291)
292
293EnableR52_1_0:
294(
295  Data.Set EAXI:0x4190054C %LE %Long &rtuStartAddr
296  Data.Set EAXI:0x41900540 %LE %Long 0x1
297  Data.Set EAXI:0x41900544 %LE %Long 0x1
298  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
299  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
300  Data.Set EAXI:0x41850050 %LE %Long 0x1C
301  RETURN
302)
303
304EnableR52_1_1:
305(
306  Data.Set EAXI:0x4190056C %LE %Long &rtuStartAddr
307  Data.Set EAXI:0x41900560 %LE %Long 0x1
308  Data.Set EAXI:0x41900564 %LE %Long 0x1
309  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
310  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
311  Data.Set EAXI:0x41850050 %LE %Long 0x18
312  RETURN
313)
314
315EnableR52_1_2:
316(
317  Data.Set EAXI:0x4190058C %LE %Long &rtuStartAddr
318  Data.Set EAXI:0x41900580 %LE %Long 0x1
319  Data.Set EAXI:0x41900584 %LE %Long 0x1
320  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
321  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
322  Data.Set EAXI:0x41850050 %LE %Long 0x10
323  RETURN
324)
325
326EnableR52_1_3:
327(
328  Data.Set EAXI:0x419005A0 %LE %Long 0x1
329  Data.Set EAXI:0x419005A4 %LE %Long 0x1
330  Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
331  Data.Set EAXI:0x41900000 %LE %Long 0xA50F
332  Data.Set EAXI:0x419005AC %LE %Long &rtuStartAddr
333  Data.Set EAXI:0x41850050 %LE %Long 0x0
334  RETURN
335)
336