1.. _phyboard_pollux:
2
3phyBOARD-Pollux i.MX8M Plus
4###########################
5
6Overview
7********
8
9The phyBOARD-Pollux is based upon the phyCORE-i.MX8M Plus SOM which is based on
10the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one
11Coretex-M7 core for real time applications like Zephyr. The phyBOARD-Pollux
12can be used for various applications like SmartHomes, Industry 4.0, IoT etc.
13It features a lots of interfaces and computing capacity. It can be used as
14a reference, to develop or in the final product too.
15
16
17Board features:
18
19- Memory:
20
21   - RAM: 256MB - 8GB LPDDR4
22   - EEPROM: 4kB - 32kB
23   - eMMC: 4GB - 64GB (eMMC 5.1)
24   - SPI NOR Flash: 4MB - 256MB
25- Interfaces:
26
27   - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support)
28   - USB: 2x 3.0 Host
29   - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex
30   - CAN: 2x CAN FD
31   - Digital I/O: via Expansion Connector
32   - PCIe: 1x miniPCIe
33   - MMX/SD/SDIO: microSD slot
34   - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI
35   - Audio: SAI
36   - Camera: 2x MIPI CSI-2 (phyCAM-M)
37   - Expansion Bus: I2C, SPI, SDIO, UART, USB
38   - JTAG: via PEB-EVAL-01
39- LEDs:
40
41   - 1x Multicolor Status LED via I2C
42
43
44.. image:: img/Phyboard_Pollux.jpg
45   :width: 720px
46   :align: center
47   :height: 405px
48   :alt: phyBOARD-Pollux
49
50More information about the board can be found at the `PHYTEC website`_.
51
52Supported Features
53==================
54
55The Zephyr phyboard_polis board configuration supports the following hardware
56features:
57
58+-----------+------------+------------------------------------+
59| Interface | Controller | Driver/Component                   |
60+===========+============+====================================+
61| NVIC      | on-chip    | nested vector interrupt controller |
62+-----------+------------+------------------------------------+
63| SYSTICK   | on-chip    | systick                            |
64+-----------+------------+------------------------------------+
65| CLOCK     | on-chip    | clock_control                      |
66+-----------+------------+------------------------------------+
67| PINMUX    | on-chip    | pinmux                             |
68+-----------+------------+------------------------------------+
69| UART      | on-chip    | serial port-polling;               |
70|           |            | serial port-interrupt              |
71+-----------+------------+------------------------------------+
72| GPIO      | on-chip    | GPIO output                        |
73|           |            | GPIO input                         |
74+-----------+------------+------------------------------------+
75
76The default configuration can be found in the defconfig file:
77:zephyr_file:`boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig`.
78
79It's recommended to disable peripherals used by the M7-Core on the host running
80on the Linux host. Other hardware features are not currently supported with
81Zephyr on the M7-Core.
82
83Connections and IOs
84===================
85
86The following Compontens are tested and working correctly.
87
88UART
89----
90
91+-----------------+----------+----------------------------+
92| Board Name      | SoM Name | Usage                      |
93+=================+==========+============================+
94| Debug USB (A53) | UART1    | UART Debug Console via USB |
95+-----------------+----------+----------------------------+
96| Wo WiFi Module  | UART3    | UART to WiFi/BLE Module    |
97+-----------------+----------+----------------------------+
98| Debug USB (M7)  | UART4    | UART Debug Console via USB |
99+-----------------+----------+----------------------------+
100
101.. note::
102  The WiFi/BLE Module connected to UART3 isn't working with Zephyr yet. UART3
103  can also be used through pin 31(RX) and 33(TX) of connector X6.
104
105GPIO
106----
107
108The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree
109created by NXP and can be found at
110:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the phyBOARD-Polis
111can be found at the `PHYTEC website`_.
112
113Programming and Debugging
114*************************
115
116The i.MX8MP does not have a separate flash for the M7-Core. Because of this
117the A53-Core has to load the program for the M7-Core to the right memory
118address, set the PC and start the processor.
119
120The M7 can use up to 3 different RAMs (currently, only two configurations are
121supported: ITCM and DDR). These are the memory mapping for A53 and M7:
122
123+---------+-----------------------+------------------------+-----------------------+-------+
124| Region  | Cortex-A53            | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus)  | Size  |
125+=========+=======================+========================+=======================+=======+
126| OCRAM   | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF  | 0x00900000-0x0098FFFF | 576KB |
127+---------+-----------------------+------------------------+-----------------------+-------+
128| DTCM    | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF  |                       | 128KB |
129+---------+-----------------------+------------------------+-----------------------+-------+
130| ITCM    | 0x007E0000-0x007FFFFF |                        | 0x00000000-0x0001FFFF | 128KB |
131+---------+-----------------------+------------------------+-----------------------+-------+
132| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF  | 0x00180000-0x00188FFF | 36KB  |
133+---------+-----------------------+------------------------+-----------------------+-------+
134| DDR     | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF  | 0x80000000-0x801FFFFF | 2MB   |
135+---------+-----------------------+------------------------+-----------------------+-------+
136
137For more information about memory mapping see the
138`i.MX 8M Plus Applications Processor Reference Manual`_  (section 2.1 to 2.3)
139
140At compilation time you have to choose which memory region will be used. This
141configuration is done in the devicetree and the defconfig / the config of your
142program.
143
144**By default Zephyr will use the TCM memory region.** You can configure it
145to use the DDR region. In the devicetree overwrite you can select both options.
146
147.. code-block:: DTS
148
149   chosen {
150      /* TCM */
151      zephyr,flash = &itcm;
152      zephyr,sram = &dtcm;
153   };
154
155
156.. code-block:: DTS
157
158   chosen {
159      /* DDR */
160      zephyr,flash = &ddr_code;
161      zephyr,sram = &ddr_sys;
162   };
163
164
165And in the prj.conf the configuration to the **DDR** memory region:
166
167.. code-block:: cfg
168
169   CONFIG_CODE_DDR=y
170   CONFIG_CODE_ITCM=n
171
172Connecting to the Serial Console
173================================
174
175A serial console for both the application CPU and the Cortex M7 coprocessor are
176available via the onboard dual USB-to-UART converter. If you use Linux, create a
177udev rule (as ``root``) to fix a permission issue when not using root for
178flashing.
179
180.. code-block:: console
181
182   # echo 'ATTR{idProduct}=="0a70", ATTR{idVendor}=="10c4", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-usb-uart.rules
183
184Reload the rules and replug the device.
185
186.. code-block:: console
187
188   $ sudo udevadm control --reload-rules
189
190Finally, unplug and plug the board again for the rules to take effect.
191
192Connect to the console via your favorite terminal program. For example:
193
194.. code-block:: console
195
196   $ minicom -D /dev/ttyUSB1 -b 115200
197
198Flashing and Debugging via JTAG
199===============================
200
201The phyBOARD-Pollux can be debugged using a JTAG or SWD debug adapter. A Segger
202JLink can be connected to the compatible JTAG connector on Phytec's
203``PEB-EVAL-01`` shield.
204
205.. figure:: img/PEB-EVAL-01.jpg
206   :alt: PEB-EVAL-01
207   :width: 350
208
209   PEB-EVAL-01
210
211Before flashing or debugging via a JTAG debug adapter,
212the M7 core has to be switched on:
213
214.. code-block:: console
215
216   u-boot=> bootaux 0x7e0000
217
218Here is an example for the :zephyr:code-sample:`hello_world` application:
219
220.. zephyr-app-commands::
221   :zephyr-app: samples/hello_world
222   :board: phyboard_pollux/mimx8ml8/m7
223   :goals: flash
224
225The console should now show the output of the application:
226
227.. code-block:: console
228
229   *** Booting Zephyr OS build v3.7.0 ***
230   Hello World! phyboard_pollux/mimx8ml8/m7
231
232Starting a debug session is similar to flashing:
233
234.. zephyr-app-commands::
235   :zephyr-app: samples/hello_world
236   :board: phyboard_pollux/mimx8ml8/m7
237   :goals: debug
238
239Starting the M7-Core from U-Boot and Linux
240==========================================
241
242Loading binaries and starting the M7-Core is supported from Linux via remoteproc
243or from U-boot by directly copying the firmware binary. Please check the
244`phyCORE-i.MX 8M Plus BSP Manual`_ for more information.
245
246References
247==========
248
249- `i.MX 8M Plus Applications Processor Reference Manual`_
250- `phyCORE-i.MX 8M Plus BSP Manual`_
251
252.. _PHYTEC website:
253   https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/
254
255.. _i.MX 8M Plus Applications Processor Reference Manual:
256   https://www.nxp.com/webapp/Download?colCode=IMX8MPRM
257
258.. _JLink Software:
259   https://www.segger.com/downloads/jlink/
260
261.. _phyCORE-i.MX 8M Plus BSP Manual:
262   https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/imx8mp.html
263