1 /* 2 * Copyright (c) 2016 Piotr Mienkowski 3 * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com> 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** @file 8 * @brief System module to support early Atmel SAM V71 MCU configuration 9 */ 10 11 #include <zephyr/device.h> 12 #include <zephyr/init.h> 13 #include <soc.h> 14 #include <zephyr/arch/cpu.h> 15 16 /** 17 * @brief Perform SoC configuration at boot. 18 * 19 * This should be run early during the boot process but after basic hardware 20 * initialization is done. 21 */ atmel_samv71_config(void)22void atmel_samv71_config(void) 23 { 24 if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) { 25 /* Disable ERASE function on PB12 pin, this is controlled 26 * by Bus Matrix 27 */ 28 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; 29 } 30 31 /* In Cortex-M based SoCs JTAG interface can be used to perform 32 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug 33 * interface therefore there is no harm done by disabling the JTAG TDI 34 * pin by default. 35 */ 36 /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix 37 */ 38 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; 39 40 if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) { 41 /* Disable PCK3 clock used by ETM module */ 42 PMC->PMC_SCDR = PMC_SCDR_PCK3; 43 while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { 44 ; 45 } 46 /* Select PLLA clock as PCK3 clock */ 47 PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; 48 /* Enable PCK3 clock */ 49 PMC->PMC_SCER = PMC_SCER_PCK3; 50 /* Wait for PCK3 setup to complete */ 51 while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { 52 ; 53 } 54 /* Enable TDO/TRACESWO function on PB5 pin */ 55 MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; 56 } else { 57 /* Disable TDO/TRACESWO function on PB5 pin */ 58 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; 59 } 60 } 61
