1 /*
2  * Copyright (c) 2013-2015 Wind River Systems, Inc.
3  * Copyright (c) 2016 Intel Corporation.
4  * Copyright (c) 2017 Justin Watson
5  * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
6  * Copyright (c) 2023 Basalte bv
7  *
8  * SPDX-License-Identifier: Apache-2.0
9  */
10 
11 /**
12  * @file
13  * @brief Atmel SAM4E MCU series initialization code
14  *
15  * This module provides routines to initialize and support board-level hardware
16  * for the Atmel SAM4E series processor.
17  */
18 
19 #include <soc.h>
20 #include <soc_pmc.h>
21 #include <soc_supc.h>
22 
23 /**
24  * @brief Setup various clock on SoC at boot time.
25  *
26  * Setup the SoC clocks according to section 28.12 in datasheet.
27  *
28  * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
29  * It is assumed that the relevant registers are at their reset value.
30  */
clock_init(void)31 static ALWAYS_INLINE void clock_init(void)
32 {
33 	/* Switch the main clock to the internal OSC with 12MHz */
34 	soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
35 
36 	/* Switch MCK (Master Clock) to the main clock */
37 	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
38 
39 	EFC->EEFC_FMR = EEFC_FMR_FWS(0);
40 
41 	soc_pmc_enable_clock_failure_detector();
42 
43 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
44 		soc_supc_slow_clock_select_crystal_osc();
45 	}
46 
47 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
48 		/*
49 		 * Setup main external crystal oscillator.
50 		 */
51 
52 		/* We select maximum setup time.
53 		 * While start up time could be shortened
54 		 * this optimization is not deemed
55 		 * critical now.
56 		 */
57 		soc_pmc_switch_mainck_to_xtal(false, 0xff);
58 	}
59 
60 	/*
61 	 * Set FWS (Flash Wait State) value before increasing Master Clock
62 	 * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
63 	 * This is set to the highest number of read cycles because it won't
64 	 * hurt lower clock frequencies. However, a high frequency with too
65 	 * few read cycles could cause flash read problems. FWS 5 (6 cycles)
66 	 * is the safe setting for all of this SoCs usable frequencies.
67 	 */
68 	EFC->EEFC_FMR = EEFC_FMR_FWS(5);
69 
70 	/*
71 	 * Setup PLLA
72 	 */
73 	soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
74 			      CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
75 
76 	/*
77 	 * Final setup of the Master Clock
78 	 */
79 
80 	/* prescaler has to be set before PLL lock */
81 	soc_pmc_mck_set_prescaler(1);
82 
83 	/* Select PLL as Master Clock source. */
84 	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
85 
86 	/* Disable internal fast RC if we have an external crystal oscillator */
87 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
88 		soc_pmc_osc_disable_fastrc();
89 	}
90 }
91 
soc_reset_hook(void)92 void soc_reset_hook(void)
93 {
94 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
95 		/*
96 		 * Instruct CPU to enter Wait mode instead of Sleep mode to
97 		 * keep Processor Clock (HCLK) and thus be able to debug
98 		 * CPU using JTAG.
99 		 */
100 		soc_pmc_enable_waitmode();
101 	}
102 	/* Setup system clocks. */
103 	clock_init();
104 }
105