Home
last modified time | relevance | path

Searched +full:is +full:- +full:ram (Results 1 – 25 of 741) sorted by relevance

12345678910>>...30

/Zephyr-latest/include/zephyr/arch/common/
Dpm_s2ram.h28 * This function is passed as argument and called by @ref arch_pm_s2ram_suspend
31 * This function never returns if the system is powered off. If the operation
32 * cannot be performed a proper value is returned and the code must take care
35 * @retval none The system is powered off.
36 * @retval -EBUSY The system is busy and cannot be powered off at this time.
37 * @retval -errno Other error codes.
44 * This function is used on suspend-to-RAM (S2RAM) to save the CPU context in
45 * (retained) RAM before powering the system off using the provided function.
46 * This function is usually called from the PM subsystem / hooks.
48 * The CPU context is usually the minimum set of CPU registers which content
[all …]
/Zephyr-latest/snippets/ram-console/
DREADME.rst1 .. _snippet-ram-console:
3 RAM Console Snippet (ram-console)
6 .. code-block:: console
8 west build -S ram-console [...]
13 This snippet redirects console output to a RAM buffer. The RAM console
14 buffer is a global array located in RAM region by default, whose address
15 is unknown before building. The RAM console driver also supports using
16 a dedicated section for the RAM console buffer with prefined address.
18 How to enable RAM console buffer section
21 Add board dts overlay to this snippet to add property ``zephyr,ram-console``
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Dnxp,flexram.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP FlexRAM on-chip ram controller
17 flexram,has-magic-addr:
22 on arbitrary address access in any on chip RAM region.
24 flexram,num-ram-banks:
28 Number of RAM banks in the SOC ram array
30 flexram,bank-size:
34 Size of each RAM bank in KB
36 flexram,bank-spec:
39 Custom mapping of runtime RAM bank partitions. If this
[all …]
/Zephyr-latest/include/zephyr/arch/mips/
Dlinker.ld6 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/linker/linker-defs.h>
16 #include <zephyr/linker/linker-tool.h>
18 #define ROMABLE_REGION RAM
19 #define RAMABLE_REGION RAM
27 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
32 REGION_ALIAS("REGION_TEXT", RAM);
33 REGION_ALIAS("REGION_RODATA", RAM);
34 REGION_ALIAS("REGION_DATA_VMA", RAM);
35 REGION_ALIAS("REGION_DATA_LMA", RAM);
[all …]
/Zephyr-latest/include/zephyr/arch/x86/
Dmemory.ld2 * Copyright (c) 2011-2014, Wind River Systems, Inc.
3 * Copyright (c) 2019-2020 Intel Corp.
5 * SPDX-License-Identifier: Apache-2.0
11 * By default, the kernel is linked at its physical address and all addresses
12 * are in RAM.
14 * If CONFIG_XIP is enabled, then another MEMORY region is declared for ROM,
15 * and this is where the Zephyr image is booted from. The linker LMAs and VMAs
17 * in RAM and are copied from flash at boot. Text/rodata linked in-place in
20 * If CONFIG_MMU is enabled, then the ROM region in MEMORY is used to set the
23 * Setting LMAs here helps let QEMU or any other ELF-aware loader know where to
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
12 This enables support for an external SPI RAM chip, connected in
15 menu "SPI RAM config"
23 regions. If the region of desired capability is exhausted,
34 bool "Run memory test on SPI RAM initialization"
40 prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
53 prompt "Type of SPI RAM chip in use"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
[all …]
/Zephyr-latest/kernel/
DKconfig.vm3 # SPDX-License-Identifier: Apache-2.0
22 By default, this is the same as the DT_CHOSEN_Z_SRAM physical base SRAM
23 address from DTS, in which case RAM will be identity-mapped. Some
24 architectures may require RAM to be mapped in this way; they may have
25 just one RAM region and doing this makes linking much simpler, as
26 at least when the kernel boots all virtual RAM addresses are the same
28 this for non-pinned page frames).
30 Otherwise, if RAM isn't identity-mapped:
31 1. It is the architecture's responsibility to transition the
35 the kernel's address space, such as not overlapping physical RAM
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
20 # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
29 This option is selected by a variable of which soc, and will
35 This option is selected by a variable of which soc, and will
41 This option is automatically selected by variant soc and sets
47 This option is automatically selected by variant soc and sets
105 bool "Flash frequency is 48MHz"
112 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
118 On IT81202 (128-pins package), the pins of GPIO group K and L aren't
119 bonding with pad. So we configure these pins as internal pull-down
[all …]
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
22 * *must* be in the Flash memory space: it is not permitted to execute from RAM addresses, only
23 * through ILM mappings into RAM.
25 * When a RAM block is configured as ILM, accesses to addresses matching the corresponding Scratch
26 * SRAM address register (SCARn{H,M,L}) are redirected to the corresponding ILM block in RAM.
27 * If SCAR0 (corresponding to ILM0) has the value 0x8021532 and ILM0 is enabled, then instruction
29 * 0x80100000..0x80101000 (the first 4k block of RAM).
31 * Instruction fetch from Flash is normally cacheable, but configuring ILM for a region makes that
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
[all …]
/Zephyr-latest/subsys/demand_paging/backing_store/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
11 This option is chosen when the backing store will be implemented in
13 hardware-dependent.
16 bool "RAM-based test backing store"
18 This implements a backing store using physical RAM pages that the
19 Zephyr kernel is otherwise unaware of. It is intended for
23 bool "Flash-based backing store on qemu_x86_tiny"
33 bool "Backing store for on-demand linker section using semihosting"
36 This is used to do on-demand paging of code and data marked with
38 zephyr.bin on the host is used to retrieve needed data with the
[all …]
/Zephyr-latest/include/zephyr/display/
Dssd16xx.h4 * SPDX-License-Identifier: Apache-2.0
13 * SSD16xx RAM type for direct RAM access
16 /** The black RAM buffer. This is typically the buffer used to
21 /* The red RAM buffer. This is typically the old frame buffer
30 * RAM.
33 * @param ram_type Type of RAM to read from
/Zephyr-latest/include/zephyr/arch/nios2/
Dlinker.ld4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/linker/linker-defs.h>
17 #include <zephyr/linker/linker-tool.h>
24 * SOC-specific linker script. All of these values can be found defined
31 * _RAM_ADDR Beginning of RAM
32 * _RAM_SIZE Size of RAM in bytes
36 * 1. Non-XIP systems where the reset vector is at the beginning of RAM
38 * 2. XIP systems where the reset vector is at the beginning of ROM and
39 * the exception vector is in RAM
51 #define ROMABLE_REGION RAM
[all …]
/Zephyr-latest/samples/boards/st/power_mgmt/suspend_to_ram/
DREADME.rst1 .. zephyr:code-sample:: stm32_pm_suspend_to_ram
2 :name: Suspend to RAM
3 :relevant-api: subsys_pm_device_runtime
5 Use suspend to RAM low power mode on STM32.
10 This sample is a minimum application to demonstrate basic power management
13 SPI loopback is also available but not yet implemented for Suspend To RAM PM
16 .. _stm32-pm-suspend-to-ram-sample-requirements:
23 in core sleep states, as LPTIM (:dtcompatible:`st,stm32-lptim`).
25 for LPTIM (which is disabled). The board shall also have RAM retention to be
33 .. zephyr-app-commands::
[all …]
/Zephyr-latest/soc/nxp/lpc/lpc55xxx/
DKconfig.defconfig2 # SPDX-License-Identifier: Apache-2.0
20 DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
29 # By default, CMSIS SystemInit will enable the clock to these RAM banks.
30 # Disable this Kconfig to leave the ram banks untouched out of reset.
34 # Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
35 # By default, USB RAM is assumed to be present.
36 # Disable this Kconfig in case there is no dedicated USB RAM.
/Zephyr-latest/boards/native/nrf_bsim/doc/
Dnrf54l15bsim.rst15 To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
30 Unlike real nRF54L15 devices, the nrf54l15bsim target has unlimited RAM, and code does not
32 of available RAM and RRAM either can be simulated using the nrf54l15bsim.
48 * GRTC (Global Real-time Counter)
51 * RRAMC (Resistive RAM Controller)
59 For more information on what is modeled to which level of detail,
79 TrustZone, TF-M and other security considerations
82 ARM's TrustZone is not modeled in this board. This means that:
84 * There is no differentiation between secure and non secure execution states or bus accesses.
85 * All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
[all …]
/Zephyr-latest/samples/net/zperf/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
7 bool "Relocate networking code into RAM"
10 Relocate networking code into RAM when running the zperf
12 RAM.
17 string "Networking code RAM location"
18 default "RAM"
26 # device stack. The scope of these options is limited to USB samples in project
/Zephyr-latest/modules/mbedtls/configs/
Dconfig-coap.h2 * Minimal configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites
4 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
5 * SPDX-License-Identifier: Apache-2.0
11 * http://www.apache.org/licenses/LICENSE-2.0
14 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
19 * This file is part of mbed TLS (https://tls.mbed.org)
22 * Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
24 * - no bignum, no PK, no X509
25 * - fully modern and secure (provided the pre-shared keys have high entropy)
26 * - very low record overhead with CCM-8
[all …]
Dconfig-suite-b.h2 * \file config-suite-b.h
8 * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
10 * This file is provided under the Apache License 2.0, or the
20 * http://www.apache.org/licenses/LICENSE-2.0
23 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
33 * This program is free software; you can redistribute it and/or modify
38 * This program is distributed in the hope that it will be useful,
45 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
53 * - no RSA or classic DH, fully based on ECC
54 * - optimized for low RAM usage
[all …]
Dconfig-ccm-psk-tls1_2.h2 * \file config-ccm-psk-tls1_2.h
4 * \brief Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
8 * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
10 * This file is provided under the Apache License 2.0, or the
20 * http://www.apache.org/licenses/LICENSE-2.0
23 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
33 * This program is free software; you can redistribute it and/or modify
38 * This program is distributed in the hope that it will be useful,
45 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
50 * Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
[all …]
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dnrf52840dk_nrf52840_ram_disk_region.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* The SRAM is defined for nrf52840 in DTS to take entire 256KiB
8 * of RAM there is. We need some for the Disk, so we need to
11 /delete-node/ &sram0;
16 /* This is defined based on dts and dtsi files for
18 * change the size, what we have to do is to remove
19 * the sram0 definition, which is a combined result
22 * The first one is reduced in size original sram0:
25 compatible = "mmio-sram";
28 /* The second one is 64kiB region taken out of SRAM,
[all …]
/Zephyr-latest/include/zephyr/arch/x86/intel64/
Dlinker.ld2 * Copyright (c) 2019-2021 Intel Corp.
3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/linker/linker-defs.h>
7 #include <zephyr/linker/linker-tool.h>
9 #define ROMABLE_REGION RAM
10 #define RAMABLE_REGION RAM
16 * the kernel is just one blob with the same RWX permissions on all RAM
29 * The "locore" must be in the 64K of RAM, so that 16-bit code (with
30 * segment registers == 0x0000) and 32/64-bit code agree on addresses.
31 * ... there is no 16-bit code yet, but there will be when we add SMP.
[all …]
/Zephyr-latest/samples/subsys/fs/format/
DREADME.rst1 .. zephyr:code-sample:: fs-format
3 :relevant-api: file_system_api
15 * FAT file system on RAM disk
22 The Flash scenario is supported on the nrf52dk/nrf52832 board.
23 The RAM disk scenario is supported on the mimxrt1064_evk board.
24 To build the RAM disk sample, the configuration :file:`prj_ram.conf` needs to be used by setting
29 .. zephyr-app-commands::
30 :zephyr-app: samples/subsys/fs/format
35 The RAM disk sample for the MIMXRT1064-EVK board can be built as follow:
37 .. zephyr-app-commands::
[all …]
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
35 bool "LPC54114 Cortex-M0 second core"
44 This is the address the second core will boot from. Additionally this
45 address is where we will copy the SECOND_IMAGE to. We default this to
49 DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
54 default "-0x20010000+\
65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
66 will enable the clock to this RAM bank. Disable this Kconfig to leave
67 this ram bank untouched out of reset.
/Zephyr-latest/drivers/bbram/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 bool "Battery-backed RAM (BBRAM) drivers"
7 Enable BBRAM (battery-backed RAM) driver configuration.
12 module-str = bbram
16 bool "Battery-backed RAM shell"
23 # In STM32, BBRAM is a part of RTC. In this case init priority must be
26 # MCP7940N is an I2C device, therefore the init priority must be
/Zephyr-latest/drivers/console/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
5 # SPDX-License-Identifier: Apache-2.0
24 This is an option to be enabled by console drivers to signal
74 the module for UART console is in use now. If the interval of console
76 as UART_CONSOLE_INPUT_EXPIRED_TIMEOUT, the power management module is
79 organize input message if CONFIG_PM is enabled.
86 Fixed amount of time which unit is milliseconds to keep the UART
95 Useful in board bring-up if there aren't any working serial
99 DT_CHOSEN_Z_RAM_CONSOLE := zephyr,ram-console
102 bool "Use RAM console"
[all …]

12345678910>>...30