1.. _nrf54l15bsim:
2
3NRF54L15 simulated boards (BabbleSim)
4#####################################
5
6.. contents::
7   :depth: 1
8   :backlinks: entry
9   :local:
10
11
12Overview
13********
14
15To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
16``nrf54l15bsim/nrf54l15/cpuapp``.
17
18This uses `BabbleSim`_ to simulate the radio activity, and the
19:ref:`POSIX architecture<Posix arch>` and the `native simulator`_ to
20run applications natively on the development system. This has the benefit of
21providing native code execution performance and easy debugging using
22native tools, but inherits :ref:`its limitations <posix_arch_limitations>`.
23
24Just like for the nrf54l15dk target,
25the nrf54l15bsim/nrf54l15/cpuapp build target provides support for the application core,
26on the simulated nRF54L15 SOC.
27
28.. note::
29
30   Unlike real nRF54L15 devices, the nrf54l15bsim target has unlimited RAM, and code does not
31   occupy its RRAM. Therefore, as the nRF54L15, nRF54L10 and nRF54L05 SOCs only differ in the amount
32   of available RAM and RRAM either can be simulated using the nrf54l15bsim.
33
34.. note::
35
36   This simulated target does **not** yet support targeting the cpuflpr core.
37
38This boards include models of some of the nRF54L15 SOC peripherals:
39
40* AAR (Accelerated Address Resolver)
41* CCM (AES CCM mode encryption)
42* CLOCK (Clock control)
43* DPPI (Distributed Programmable Peripheral Interconnect)
44* ECB (AES electronic codebook mode encryption)
45* EGU (Event Generator Unit)
46* FICR (Factory Information Configuration Registers)
47* GPIO & GPIOTE
48* GRTC (Global Real-time Counter)
49* PPIB (PPI Bridge)
50* RADIO
51* RRAMC (Resistive RAM Controller)
52* RTC (Real Time Counter)
53* TEMP (Temperature sensor)
54* TIMER
55* UARTE (UART with Easy DMA)
56* UICR (User Information Configuration Registers)
57
58and will use the same drivers as the nrf54l15dk targets for these.
59For more information on what is modeled to which level of detail,
60check the `HW models implementation status`_.
61
62.. _BabbleSim:
63   https://BabbleSim.github.io
64
65.. _native simulator:
66   https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md
67
68.. _HW models implementation status:
69   https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_impl_status.md
70
71
72Building for, and using this board
73**********************************
74
75You can follow the instructions from the :ref:`nrf52_bsim board <nrf52bsim_build_and_run>`.
76Simply change the board/target appropriately when building.
77
78
79TrustZone, TF-M and other security considerations
80*************************************************
81
82ARM's TrustZone is not modeled in this board. This means that:
83
84* There is no differentiation between secure and non secure execution states or bus accesses.
85* All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
86  own interconnect master ports can, in principle, access any other peripheral or RAM area.
87* There is no nrf54l15bsim/nrf54l15/cpuapp/ns board/build target, or possibility of mixing secure
88  and non-secure images.
89* Currently there is no model of the SPU, and therefore neither RRAM, RAM areas or peripherals
90  can be labeled as restricted for secure or non secure access.
91* TF-M cannot be used.
92
93Note that the CRACEN peripheral is not modeled.
94As crypto library, Mbed TLS can be used with its SW crypto backend.
95As entropy driver, the :dtcompatible:`zephyr,native-posix-rng` is enabled by default.
96