Lines Matching +full:is +full:- +full:ram

2  * Copyright (c) 2011-2014, Wind River Systems, Inc.
3  * Copyright (c) 2019-2020 Intel Corp.
5  * SPDX-License-Identifier: Apache-2.0
11  * By default, the kernel is linked at its physical address and all addresses
12  * are in RAM.
14  * If CONFIG_XIP is enabled, then another MEMORY region is declared for ROM,
15  * and this is where the Zephyr image is booted from. The linker LMAs and VMAs
17  * in RAM and are copied from flash at boot. Text/rodata linked in-place in
20  * If CONFIG_MMU is enabled, then the ROM region in MEMORY is used to set the
23  * Setting LMAs here helps let QEMU or any other ELF-aware loader know where to
34 /* Bounds of physical RAM from DTS */
38 /* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily
39  * the same as its physical location, although an identity mapping for RAM
40  * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.
44 #define KERNEL_RAM_SIZE   (CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)
45 #define PHYS_RAM_AVAIL    (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
48 #define KERNEL_RAM_SIZE   (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
51 /* "kernel RAM" for linker VMA allocations starts at the offset */
60   /* "ROM" is flash, we leave rodata and text there and just copy in data.
61    * Board-level DTS must specify a flash region that doesn't overlap with
62    * sram0, so that DT_PHYS_LOAD_ADDR is set.
64   #define FLASH_ROM_SIZE      (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - ROM_END_OFFSET)
67   /* Physical RAM location where the kernel image is loaded */
76 #define LOCORE_SIZE         (0x10000 - LOCORE_BASE)
79 #error Virtual kernel linking is not yet implemented for 64-bit
87      * or copied into physical RAM by a loader (MMU)
93     /* Linear address range to link the kernel. If non-XIP, everything is
97     RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
101     /* Special low-memory area for bootstrapping other CPUs from real mode */
105      * On 32-bit x86, fake memory area for build-time IDT generation data.
106      * 64-bit doesn't use this, interrupts are all managed at runtime.
108      * It doesn't matter where this region goes as it is stripped from the