4  * SPDX-License-Identifier: Apache-2.0
20  * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
22  * *must* be in the Flash memory space: it is not permitted to execute from RAM addresses, only
23  * through ILM mappings into RAM.
25  * When a RAM block is configured as ILM, accesses to addresses matching the corresponding Scratch
26  * SRAM address register (SCARn{H,M,L}) are redirected to the corresponding ILM block in RAM.
27  * If SCAR0 (corresponding to ILM0) has the value 0x8021532 and ILM0 is enabled, then instruction
29  * 0x80100000..0x80101000 (the first 4k block of RAM).
31  * Instruction fetch from Flash is normally cacheable, but configuring ILM for a region makes that
32  * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
53  * SCAR registers contain 20-bit addresses in three registers, with one set
76 	return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0;  in is_block_aligned()
83 		return -EFAULT; /* Not in RAM */  in it8xxx2_configure_ilm_block()
85 	const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;  in it8xxx2_configure_ilm_block()
87 	if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) {  in it8xxx2_configure_ilm_block()
88 		return -EFAULT; /* Past the end of RAM */  in it8xxx2_configure_ilm_block()
91 		     "Flash is assumed to be aligned to SCAR register width");  in it8xxx2_configure_ilm_block()
92 	if (((uintptr_t)flash_addr - FLASH_BASE) & ~GENMASK(19, 0)) {  in it8xxx2_configure_ilm_block()
93 		return -EFAULT; /* Address doesn't fit in the SCAR */  in it8xxx2_configure_ilm_block()
97 		return -EFAULT;  in it8xxx2_configure_ilm_block()
100 	LOG_DBG("Enabling ILM%d %p -> %p, copy %d", dirmap_index, flash_addr, ram_addr, copy_sz);  in it8xxx2_configure_ilm_block()
102 	volatile struct scar_reg *const scar = config->scar_regs[dirmap_index];  in it8xxx2_configure_ilm_block()
106 	/* Ensure scratch RAM for block data access is enabled */  in it8xxx2_configure_ilm_block()
107 	scar->h = SCARH_ENABLE;  in it8xxx2_configure_ilm_block()
108 	/* Copy block contents from flash into RAM */  in it8xxx2_configure_ilm_block()
111 	scar->l = (uintptr_t)flash_addr & GENMASK(7, 0);  in it8xxx2_configure_ilm_block()
112 	scar->m = ((uintptr_t)flash_addr & GENMASK(15, 8)) >> 8;  in it8xxx2_configure_ilm_block()
119 	scar->h = scarh_value;  in it8xxx2_configure_ilm_block()
129 		 "ILM physical base address (%p) must be 4k-aligned", __ilm_ram_start);  in it8xxx2_ilm_init()
131 		 "ILM flash base address (%p) must be 4k-aligned", __ilm_flash_start);  in it8xxx2_ilm_init()
135 	LOG_DBG("ILM init %p-%p -> %p-%p", __ilm_flash_start, __ilm_flash_end, __ilm_ram_start,  in it8xxx2_ilm_init()
140 			(uintptr_t)__ilm_flash_start + (block_base - (uintptr_t)__ilm_ram_start);  in it8xxx2_ilm_init()
142 		 * Part of the target RAM block might be used for non-code data; avoid overwriting  in it8xxx2_ilm_init()
145 		size_t used_size = MIN((uintptr_t)__ilm_flash_end - flash_base, ILM_BLOCK_SIZE);  in it8xxx2_ilm_init()
146 		int rv = it8xxx2_configure_ilm_block(dev->config, (void *)block_base,  in it8xxx2_ilm_init()
209 	     "Wrong number of SCAR registers defined for RAM size");