Lines Matching +full:is +full:- +full:ram

15 To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
30    Unlike real nRF54L15 devices, the nrf54l15bsim target has unlimited RAM, and code does not
32    of available RAM and RRAM either can be simulated using the nrf54l15bsim.
48 * GRTC (Global Real-time Counter)
51 * RRAMC (Resistive RAM Controller)
59 For more information on what is modeled to which level of detail,
79 TrustZone, TF-M and other security considerations
82 ARM's TrustZone is not modeled in this board. This means that:
84 * There is no differentiation between secure and non secure execution states or bus accesses.
85 * All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
86   own interconnect master ports can, in principle, access any other peripheral or RAM area.
87 * There is no nrf54l15bsim/nrf54l15/cpuapp/ns board/build target, or possibility of mixing secure
88   and non-secure images.
89 * Currently there is no model of the SPU, and therefore neither RRAM, RAM areas or peripherals
91 * TF-M cannot be used.
93 Note that the CRACEN peripheral is not modeled.
95 As entropy driver, the :dtcompatible:`zephyr,native-posix-rng` is enabled by default.