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/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8qxp.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 irqsteer: interrupt-controller@51080000 {
11 compatible = "nxp,irqsteer-intc";
13 power-domains = <&irqstr_pd>;
15 #size-cells = <0>;
16 #address-cells = <1>;
18 master0: interrupt-controller@0 {
19 compatible = "nxp,irqsteer-master";
21 interrupt-controller;
22 #interrupt-cells = <1>;
[all …]
Dnxp_imx8qm.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 irqsteer: interrupt-controller@510a0000 {
12 compatible = "nxp,irqsteer-intc";
14 power-domains = <&irqstr_pd>;
16 #size-cells = <0>;
17 #address-cells = <1>;
19 master0: interrupt-controller@0 {
20 compatible = "nxp,irqsteer-master";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
Dnxp_imx8m.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "cdns,tensilica-xtensa-lx6";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clic: interrupt-controller@0 {
25 compatible = "cdns,xtensa-core-intc";
27 interrupt-controller;
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/Zephyr-latest/dts/bindings/test/
Dvnd,interrupt-holder-extended.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Interrupt Controller with extended interrupts
6 compatible: "vnd,interrupt-holder-extended"
11 interrupts-extended:
14 interrupt-names:
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.gd32_exti2 # SPDX-License-Identifier: Apache-2.0
5 bool "GD32 Extended Interrupts and Events (EXTI) Controller"
9 Enable the GigaDevice GD32 Extended Interrupts and Events (EXTI)
Dintc_nuclei_eclic.S4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
16 * In an ECLIC, pending interrupts don't have to be cleared by hand.
17 * In vectored mode, interrupts are cleared automatically.
18 * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
34 * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
37 addi sp, sp, -16
40 /* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
52 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
72 /* Read and clear mnxti to get highest current interrupt and enable interrupts. */
Dintc_irqmp.c2 * Copyright (c) 2019-2020 Cobham Gaisler AB
4 * SPDX-License-Identifier: Apache-2.0
11 * Interrupt level 1..15 are SPARC interrupts. Interrupt level 16..31, if
12 * implemented in the interrupt controller, are IRQMP "extended interrupts".
24 * IRQMP - Multiprocessor Interrupt Controller
25 * IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support
64 volatile uint32_t *pimask = &regs->pimask[0]; in arch_irq_enable()
76 volatile uint32_t *pimask = &regs->pimask[0]; in arch_irq_disable()
88 volatile uint32_t *pimask = &regs->pimask[0]; in arch_irq_is_enabled()
100 source = regs->pextack[0] & IRQMP_PEXTACK_EID; in z_sparc_int_get_source()
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/Zephyr-latest/tests/drivers/build_all/interrupt_controller/common/boards/
Dimx8mp_evk_mimx8ml8_adsp.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Made-up devicetree to build intc_nxp_irqsteer.c, refer to:
9 * https://github.com/zephyrproject-rtos/zephyr/pull/62776#issuecomment-1727846332
14 irqsteer: interrupt-controller@30a80000 {
15 compatible = "nxp,irqsteer-intc";
18 #size-cells = <0>;
19 #address-cells = <1>;
21 master0: interrupt-controller@0 {
22 compatible = "nxp,irqsteer-master";
24 interrupt-controller;
[all …]
/Zephyr-latest/dts/riscv/
Drenode_riscv32_virt.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
17 clock-frequency = <0>;
22 hlic: interrupt-controller {
23 compatible = "riscv,cpu-intc";
24 #address-cells = <0>;
25 #interrupt-cells = <1>;
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/Zephyr-latest/dts/bindings/base/
Dbase.yaml10 - "ok" # Deprecated form
11 - "okay"
12 - "disabled"
13 - "reserved"
14 - "fail"
15 - "fail-sss"
18 type: string-array
26 reg-names:
27 type: string-array
30 interrupts:
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/Zephyr-latest/dts/riscv/efinix/
Dsapphire_soc.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 clock-frequency = <100000000>;
30 compatible = "efinix,vexriscv-sapphire", "riscv";
36 hlic: interrupt-controller {
37 compatible = "riscv,cpu-intc";
[all …]
/Zephyr-latest/dts/riscv/microchip/
Dmicrochip-miv.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 clock-frequency = <0>;
20 hlic: interrupt-controller {
21 compatible = "riscv,cpu-intc";
22 #address-cells = <0>;
23 #interrupt-cells = <1>;
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Dmpfs.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/timer/
Dandestech,machine-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Andes machine timer provides RISC-V privileged mtime and mtimecmp
10 compatible: "andestech,machine-timer"
18 interrupts-extended:
/Zephyr-latest/tests/drivers/build_all/interrupt_controller/intc_plic/
Dapp.multi_instance.overlay4 * SPDX-License-Identifier: Apache-2.0
9 plic1: interrupt-controller@8000000 {
10 riscv,max-priority = <7>;
13 interrupts-extended = <
23 interrupt-controller;
24 compatible = "sifive,plic-1.0.0";
25 #address-cells = <0x00>;
26 #interrupt-cells = <0x02>;
31 interrupts = <0x0a 1>;
32 interrupt-parent = <&plic1>;
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv32-fe310.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
[all …]
Driscv64-fu740.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
[all …]
/Zephyr-latest/snippets/xen_dom0/boards/
Drcar_spider_s4_r8a779f0_a55.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &ram;
8 /delete-node/ &hscif0;
14 * (XEN) Grant table range: 0x00000078080000-0x000000780c0000
15 * Also, add extended region 1:
16 * (XEN) Extended region 1: 0x40000000->0x47e00000
24 interrupts = <GIC_PPI 0x0 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
25 interrupt-parent = <&gic>;
31 * region for Domain-0 for every specific configuration. You can
34 * (XEN) BANK[0] 0x00000080000000-0x00000090000000 (256MB)
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/Zephyr-latest/boards/snps/nsim/arc_v/
Drmx1xx.dtsi2 #address-cells = <1>;
3 #size-cells = <1>;
6 timebase-frequency = <5000000>;
7 #address-cells = <1>;
8 #size-cells = <0>;
14 clock-frequency = <5000000>;
17 cpu0_intc: interrupt-controller {
18 compatible = "riscv,cpu-intc";
19 interrupt-controller;
20 #address-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/crypto/
Dnordic,nrf-ccm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-ccm"
14 interrupts:
17 length-field-length-8-bits:
20 Indicates whether the CCM peripheral supports the extended length
24 headermask-supported:
/Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/
Dalt_mapping.overlay4 * SPDX-License-Identifier: Apache-2.0
9 plic: interrupt-controller@c000000 {
10 riscv,max-priority = <7>;
13 interrupts-extended = <
23 interrupt-controller;
24 compatible = "sifive,plic-1.0.0";
25 #address-cells = < 0x00 >;
26 #interrupt-cells = < 0x02 >;
/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
13 // Interrupts
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
23 interrupts = <1 2 3 4 5 6>;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
[all …]
/Zephyr-latest/dts/bindings/rtc/
Dst,stm32-rtc.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-rtc"
10 - rtc.yaml
11 - rtc-device.yaml
17 calib-out-freq:
22 - 1
23 - 512
25 alarms-count:
31 alrm-exti-line:
34 Number of the Extended Interrupts and Event Controller (EXTI) interrupt
[all …]
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "starfive,fu74-g000";
21 clock-frequency = <0>;
[all …]

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