1/ {
2	#address-cells = <1>;
3	#size-cells = <1>;
4
5	cpus {
6			timebase-frequency = <5000000>;
7			#address-cells = <1>;
8			#size-cells = <0>;
9
10			cpu0: cpu@0 {
11				compatible = "snps,av5rmx", "riscv";
12				device_type = "cpu";
13				reg = <0>;
14				clock-frequency = <5000000>;
15				riscv,isa = "rv32imac_zicsr_zifencei";
16
17				cpu0_intc: interrupt-controller {
18					compatible = "riscv,cpu-intc";
19					interrupt-controller;
20					#address-cells = <0>;
21					#interrupt-cells = <1>;
22				};
23			};
24		};
25
26		soc {
27			compatible = "simple-bus";
28			ranges;
29			interrupt-parent = <&clint>;
30			#address-cells = <1>;
31			#size-cells = <1>;
32
33			clint: clint@2000000 {
34				compatible = "sifive,clint0";
35				reg = <0x2000000 0x1000>;
36				interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
37				interrupt-names = "soft0", "timer0";
38			};
39
40			mtimer: timer@200bff8 {
41				compatible = "riscv,machine-timer";
42				interrupts-extended = <&cpu0_intc 7>;
43				reg = <0x200bff8 0x8 0x2004000 0x8>;
44				reg-names = "mtime", "mtimecmp";
45			};
46
47			uart0: serial@10000000{
48				compatible = "ns16550", "snps,dw-apb-uart";
49				reg = <0x10000000 0x400>;
50				reg-shift = <2>;
51
52				/* AIA interrupt controller is not currently implemented,
53				 * so connect UART interrupt to 17th line as a stub to
54				 * make build system and test framework happy.
55				 */
56				interrupt-parent = <&cpu0_intc>;
57				interrupts = <17>;
58				clock-frequency = <50000000>;
59				status = "disabled";
60			};
61		};
62};
63