/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
			timebase-frequency = <5000000>;
			#address-cells = <1>;
			#size-cells = <0>;

			cpu0: cpu@0 {
				compatible = "snps,av5rmx", "riscv";
				device_type = "cpu";
				reg = <0>;
				clock-frequency = <5000000>;
				riscv,isa = "rv32imac_zicsr_zifencei";

				cpu0_intc: interrupt-controller {
					compatible = "riscv,cpu-intc";
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};

		soc {
			compatible = "simple-bus";
			ranges;
			interrupt-parent = <&clint>;
			#address-cells = <1>;
			#size-cells = <1>;

			clint: clint@2000000 {
				compatible = "sifive,clint0";
				reg = <0x2000000 0x1000>;
				interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
				interrupt-names = "soft0", "timer0";
			};

			uart0: serial@10000000{
				compatible = "ns16550", "snps,dw-apb-uart";
				reg = <0x10000000 0x400>;
				reg-shift = <2>;

				/* AIA interrupt controller is not currently implemented,
				 * so connect UART interrupt to 17th line as a stub to
				 * make build system and test framework happy.
				 */
				interrupt-parent = <&cpu0_intc>;
				interrupts = <17>;
				clock-frequency = <50000000>;
				status = "disabled";
			};
		};
};