Lines Matching +full:interrupts +full:- +full:extended
2 * Copyright (c) 2019-2020 Cobham Gaisler AB
4 * SPDX-License-Identifier: Apache-2.0
11 * Interrupt level 1..15 are SPARC interrupts. Interrupt level 16..31, if
12 * implemented in the interrupt controller, are IRQMP "extended interrupts".
24 * IRQMP - Multiprocessor Interrupt Controller
25 * IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support
64 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_enable()
76 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_disable()
88 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_is_enabled()
100 source = regs->pextack[0] & IRQMP_PEXTACK_EID; in z_sparc_int_get_source()
115 regs->ilevel = 0; in irqmp_init()
116 regs->ipend = 0; in irqmp_init()
117 regs->iforce0 = 0; in irqmp_init()
118 regs->pimask[0] = 0; in irqmp_init()
119 regs->piforce[0] = 0xfffe0000; in irqmp_init()