1/*
2 * Copyright (c) 2023 Efinix Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	model = "efinix,sapphire";
14	compatible = "efinix,sapphire";
15
16	chosen {
17		zephyr,sram = &ram0;
18	};
19
20	ram0: memory@F9000000 {
21		device_type = "memory";
22		reg = <0xF9000000 DT_SIZE_K(192)>;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		cpu@0 {
29			clock-frequency = <100000000>;
30			compatible = "efinix,vexriscv-sapphire", "riscv";
31			device_type = "cpu";
32			reg = <0>;
33			riscv,isa = "rv32ima_zicsr_zifencei";
34			status = "okay";
35
36			hlic: interrupt-controller {
37				compatible = "riscv,cpu-intc";
38				#address-cells = <0>;
39				#interrupt-cells = <1>;
40				interrupt-controller;
41			};
42		};
43	};
44
45	soc {
46		#address-cells = <1>;
47		#size-cells = <1>;
48		compatible = "efinix,sapphire";
49		ranges;
50
51		plic0: interrupt-controller@f8c00000 {
52			compatible = "sifive,plic-1.0.0";
53			#address-cells = <0>;
54			#interrupt-cells = <2>;
55			interrupt-controller;
56			interrupts-extended = <&hlic 11>;
57			reg = <0xf8c00000 0x0400000>;
58			riscv,max-priority = <3>;
59			riscv,ndev = <32>;
60		};
61
62		clint: clint@f8b00000 {
63			compatible = "sifive,clint0";
64			interrupts-extended = <&hlic 3 &hlic 7>;
65			reg = <0xf8b00000 0x10000>;
66		};
67
68		timer0: timer@e0002800 {
69			compatible = "efinix,sapphire-timer0";
70			reg = <0xe0002800 0x40>;
71			interrupt-parent = <&plic0>;
72			interrupts = <19 0>;
73			status = "disabled";
74		};
75
76		gpio0: gpio@f8015000 {
77			compatible = "efinix,sapphire-gpio";
78			reg = <0xf8015000 0x100>;
79			reg-names = "base";
80			ngpios = <4>;
81			gpio-controller;
82			#gpio-cells = <2>;
83			#address-cells = <1>;
84			#size-cells = <1>;
85			status = "disabled";
86		};
87
88		uart0: uart@f8010000 {
89			compatible = "efinix,sapphire-uart0";
90			interrupt-parent = <&plic0>;
91			interrupts = <1 1>;
92			reg = <0xf8010000 0x40>;
93			reg-names = "base";
94			current-speed = <115200>;
95			status = "disabled";
96		};
97
98	};
99};
100