1/*
2 * Copyright 2021, 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8#include <nxp/nxp_imx8.dtsi>
9
10/ {
11	irqsteer: interrupt-controller@510a0000 {
12		compatible = "nxp,irqsteer-intc";
13		reg = <0x510a0000 DT_SIZE_K(64)>;
14		power-domains = <&irqstr_pd>;
15
16		#size-cells = <0>;
17		#address-cells = <1>;
18
19		master0: interrupt-controller@0 {
20			compatible = "nxp,irqsteer-master";
21			reg = <0>;
22			interrupt-controller;
23			#interrupt-cells = <1>;
24			interrupts-extended = <&clic 19 0 0>;
25		};
26
27		master1: interrupt-controller@1 {
28			compatible = "nxp,irqsteer-master";
29			reg = <1>;
30			interrupt-controller;
31			#interrupt-cells = <1>;
32			interrupts-extended = <&clic 20 0 0>;
33		};
34
35		master2: interrupt-controller@2 {
36			compatible = "nxp,irqsteer-master";
37			reg = <2>;
38			interrupt-controller;
39			#interrupt-cells = <1>;
40			interrupts-extended = <&clic 21 0 0>;
41		};
42
43		master3: interrupt-controller@3 {
44			compatible = "nxp,irqsteer-master";
45			reg = <3>;
46			interrupt-controller;
47			#interrupt-cells = <1>;
48			interrupts-extended = <&clic 22 0 0>;
49		};
50
51		master4: interrupt-controller@4 {
52			compatible = "nxp,irqsteer-master";
53			reg = <4>;
54			interrupt-controller;
55			#interrupt-cells = <1>;
56			interrupts-extended = <&clic 23 0 0>;
57		};
58
59		master5: interrupt-controller@5 {
60			compatible = "nxp,irqsteer-master";
61			reg = <5>;
62			interrupt-controller;
63			#interrupt-cells = <1>;
64			interrupts-extended = <&clic 24 0 0>;
65		};
66
67		master6: interrupt-controller@6 {
68			compatible = "nxp,irqsteer-master";
69			reg = <6>;
70			interrupt-controller;
71			#interrupt-cells = <1>;
72			interrupts-extended = <&clic 25 0 0>;
73		};
74
75		master7: interrupt-controller@7 {
76			compatible = "nxp,irqsteer-master";
77			reg = <7>;
78			interrupt-controller;
79			#interrupt-cells = <1>;
80			interrupts-extended = <&clic 26 0 0>;
81		};
82	};
83};
84
85&edma0 {
86	power-domains = <&edma2_ch6_pd>, <&edma2_ch7_pd>,
87			<&edma2_ch14_pd>, <&edma2_ch15_pd>;
88};
89