Lines Matching +full:interrupts +full:- +full:extended
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "starfive,fu74-g000";
21 clock-frequency = <0>;
23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39";
35 next-level-cache = <&cachectrl>;
40 tlb-split;
41 cpu0intctrl: interrupt-controller {
42 compatible = "riscv,cpu-intc";
43 #address-cells = <0>;
44 #interrupt-cells = <1>;
45 interrupt-controller;
50 clock-frequency = <0>;
52 d-cache-block-size = <64>;
53 d-cache-sets = <64>;
54 d-cache-size = <32768>;
55 d-tlb-sets = <1>;
56 d-tlb-size = <32>;
58 i-cache-block-size = <64>;
59 i-cache-sets = <64>;
60 i-cache-size = <32768>;
61 i-tlb-sets = <1>;
62 i-tlb-size = <32>;
63 mmu-type = "riscv,sv39";
64 next-level-cache = <&cachectrl>;
69 tlb-split;
70 cpu1intctrl: interrupt-controller {
71 compatible = "riscv,cpu-intc";
72 #address-cells = <0>;
73 #interrupt-cells = <1>;
74 interrupt-controller;
85 #address-cells = <2>;
86 #size-cells = <2>;
87 #clock-cells = <1>;
88 compatible = "starfive,freedom-u74-arty", "simple-bus";
91 cachectrl: cache-controller@2010000 {
92 cache-block-size = <64>;
93 cache-level = <2>;
94 cache-sets = <2048>;
95 cache-size = <2097152>;
96 cache-unified;
97 compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
98 interrupt-parent = <&plic>;
99 interrupts = <128 1>, <131 1>, <129 1>, <130 1>;
100 /*next-level-cache = <&L40 &L36>;*/
102 reg-names = "control", "sideband";
108 reg-names = "mem";
114 reg-names = "mem";
118 compatible = "starfive,jh7100-clint", "sifive,clint0";
119 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
125 compatible = "sifive,plic-1.0.0";
126 #address-cells = <0>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9
132 riscv,max-priority = <7>;
137 compatible = "ns16550", "snps,dw-apb-uart";
138 interrupt-parent = <&plic>;
139 interrupts = <73 1>;
141 reg-shift = <2>;
143 clock-names = "baudclk", "apb_pclk";
144 clock-frequency = <100000000>;
145 current-speed = <115200>;
150 compatible = "ns16550", "snps,dw-apb-uart";
151 interrupt-parent = <&plic>;
152 interrupts = <72 1>;
154 reg-shift = <2>;
156 clock-names = "baudclk", "apb_pclk";
157 clock-frequency = <100000000>;
158 current-speed = <115200>;
163 compatible = "ns16550", "snps,dw-apb-uart";
164 interrupt-parent = <&plic>;
165 interrupts = <93 1>;
167 reg-shift = <2>;
169 clock-names = "baudclk","apb_pclk";
170 clock-frequency = <74250000>;
171 current-speed = <115200>;
176 compatible = "ns16550", "snps,dw-apb-uart";
177 interrupt-parent = <&plic>;
178 interrupts = <92 1>;
180 reg-shift = <2>;
182 clock-names = "baudclk", "apb_pclk";
183 clock-frequency = <74250000>;
184 current-speed = <115200>;