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/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton I3C controller
11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
26 /* I3C clock frequency suggestion = <PP_SCL, OD_SCL> */
30 i3c-scl-hz = <12500000>;
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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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/Zephyr-latest/dts/arm/nuvoton/npcm/
Dnpcm4.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 reg-io-width = <1>;
23 reg-io-width = <2>;
26 pcc: clock-controller@4000d000 {
27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
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/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx4.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx4/npcx4-alts-map.dtsi"
10 #include "npcx4/npcx4-miwus-wui-map.dtsi"
12 #include "npcx4/npcx4-miwus-int-map.dtsi"
14 #include "npcx4/npcx4-espi-vws-map.dtsi"
15 /* npcx4 series low-voltage io controls mapping table */
16 #include "npcx4/npcx4-lvol-ctrl-map.dtsi"
18 #include "zephyr/dt-bindings/reset/npcx4_reset.h"
26 cpu-power-states = <&suspend_to_idle0>;
29 power-states {
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/Zephyr-latest/boards/st/nucleo_h563zi/
Dnucleo_h563zi-common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <st/h5/stm32h563zitx-pinctrl.dtsi>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 compatible = "gpio-leds";
32 compatible = "gpio-keys";
41 compatible = "pwm-leds";
52 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
53 hse-bypass;
66 div-m = <2>;
67 mul-n = <120>;
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/Zephyr-latest/dts/arm/nxp/
Dnxp_rt118x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/clock/imx_ccm_rev2.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
23 #address-cells = <1>;
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Dnxp_mcxn94x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
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Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
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Dnxp_rt5xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h4 * SPDX-License-Identifier: Apache-2.0
37 /* Core clock prescaler */
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
67 * - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
68 * - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
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/Zephyr-latest/drivers/i3c/
Di3c_cdns.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/i3c.h>
461 /* Maximum i3c devices that the IP can be built with */
472 /* Target T_LOW period in open-drain mode. */
476 * MIPI I3C v1.1.1 Spec defines SDA Signal Data Hold in Push Pull max as the
484 /* command tx fifo threshold - unused */
486 /* in-band-interrupt data fifo threshold - unused */
488 /* in-band-interrupt response queue threshold */
490 /* tx data threshold - unused */
522 /* Cadence I3C/I2C Device Private Data */
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/Zephyr-latest/drivers/clock_control/
Dclock_control_npcm.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
41 /* 0x008: HFCG Prescaler */
90 /* Core clock prescaler */
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
97 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
99 #define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
101 #define FIUDIV_VAL (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1)
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/Zephyr-latest/dts/arm/st/h5/
Dstm32h5.dtsi2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
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/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
70 /* 0x008: HFCG Prescaler */
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
133 /* 0x024: Power-Down Control 7 */
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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