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/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-nrf-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nRF-specific GPIO Flags
11 * @defgroup gpio_interface_nrf nRF-specific GPIO Flags
17 * @name nRF GPIO drive flags
18 * @brief nRF GPIO drive flags
20 * Standard (S) or High (H) drive modes can be applied to both pin levels, 0 or
21 * 1. High drive mode will increase current capabilities of the pin (refer to
24 * When the pin is configured to operate in open-drain mode (wired-and), the
25 * drive mode can only be selected for the 0 level (1 is disconnected).
26 * Similarly, when the pin is configured to operate in open-source mode
[all …]
Dnordic-npm2100-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM2100-specific GPIO Flags
11 * @defgroup gpio_interface_npm2100 nPM2100-specific GPIO Flags
13 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
16 * - Bit 8: Drive strength (0=1mA, 1=6mA)
17 * - Bit 9: Debounce (0=OFF, 1=ON)
24 * @name nPM2100 GPIO drive strength flags
25 * @brief nPM2100 GPIO drive strength flags
30 /** Drive mode field mask */
34 /** Normal drive */
[all …]
Dnordic-npm6001-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM6001-specific GPIO Flags
11 * @defgroup gpio_interface_npm6001 nPM6001-specific GPIO Flags
13 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
16 * - Bit 8: Drive strength (0=NORMAL, 1=HIGH)
17 * - Bit 9: Input type (0=SCHMITT, 1=CMOS)
24 * @name nPM6001 GPIO drive strength flags
25 * @brief nPM6001 GPIO drive strength flags
30 /** Drive mode field mask */
34 /** Normal drive */
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/Zephyr-latest/dts/bindings/pinctrl/
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
32 /* Configure GPIO to push-pull mode */
33 drive-push-pull;
35 output-high;
[all …]
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
17 slew-rate = "normal";
18 drive-strength = "normal";
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
40 compatible: "nxp,rt-iocon-pinctrl"
[all …]
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
37 description: enable pull-down resistor
[all …]
Dadi,max32-pinctrl.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` are default pin configurations.
10 compatible: "adi,max32-pinctrl"
19 child-binding:
24 - name: pincfg-node.yaml
25 property-allowlist:
26 - bias-disable
27 - bias-pull-down
[all …]
Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
[all …]
Dti,cc32xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
57 - drive-open-drain: Open-drain drive mode.
[all …]
Dgd,gd32-pinctrl-afio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
47 /* configure PA9, PA10, PA11 and PA12 in analog mode */
55 for the sleep state (used in device low power mode). Note that analog mode
56 is used for low power states because it disconnects the pin pull-up/down
[all …]
Dgd,gd32-pinctrl-af.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
47 /* configure PA9, PA10, PA11 and PA12 in analog mode */
55 for the sleep state (used in device low power mode). Note that analog mode
56 is used for low power states because it disconnects the pin pull-up/down
[all …]
Dinfineon,cat1-pinctrl.yaml4 # SPDX-License-Identifier: Apache-2.0
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
30 * input-enable (input-buffer)
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Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
21 Both pins will be configured with a slow slew rate, and minimum drive
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
28 bias-pull-down: PUE=0, PE=1
29 drive-open-drain: ODE=1
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/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 /* Configure pin control bias mode for uart2 pins */
8 drive-push-pull;
12 input-enable;
16 drive-push-pull;
20 input-enable;
23 /* Configure pin control bias mode for uart5 pins */
25 drive-push-pull;
29 input-enable;
32 /* Configure pin control bias mode for i2c3 pins */
[all …]
/Zephyr-latest/boards/cypress/cy8ckit_062_ble/
Dcy8ckit_062_ble_cy8c6347-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
9 /* Configure pin control bias mode for uart5 pins */
11 drive-push-pull;
15 input-enable;
19 drive-push-pull;
23 input-enable;
27 drive-push-pull;
31 input-enable;
34 /* Configure pin control bias mode for SPI pins */
[all …]
/Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/
Dcy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
9 /* Configure pin control bias mode for uart5 pins */
11 drive-push-pull;
15 input-enable;
19 drive-push-pull;
23 input-enable;
27 drive-push-pull;
31 input-enable;
34 /* Configure pin control bias mode for SPI pins */
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,mipi-dbi-flexio-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mipi-dbi-flexio-lcdif"
8 include: [mipi-dbi-controller.yaml, base.yaml, pinctrl-device.yaml]
11 shifters-count:
17 timers-count:
23 enwr-pin:
27 Pin select for WR(8080 mode), EN(6800 mode).
29 rd-pin:
32 Pin select for RD(8080 mode), not used in 6800 mode.
34 data-pin-start:
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
36 "active-channel" (single channel mode).
38 true = Auto-Scan conversions as selected by "rr-sequence"
[all …]
/Zephyr-latest/dts/bindings/clock/
Drenesas,ra-cgc-subclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA Sub-Clock
6 compatible: "renesas,ra-cgc-subclk"
8 include: fixed-clock.yaml
11 drive-capability:
15 - 0
16 - 1
17 - 2
18 - 3
20 Sub-Clock Oscillator Drive Capability Switching
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dnrf-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 19-23: Reserved.
15 * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
16 * - 17: Clockpin enable.
17 * - 16: Pin inversion mode.
18 * - 15: Pin low power mode.
19 * - 14..11: Pin output drive configuration.
20 * - 10..9: Pin pull configuration.
[all …]
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
58 prompt "Reading mode used by the SPI flash"
61 This sets the reading mode that can be used by the SPI flash.
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 bool "SPI flash operates full-duplex with fast reading mode"
71 bool "SPI flash operates with dual data reading mode"
74 bool "SPI flash operates with quad data reading mode"
139 prompt "Flash drive strength"
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/Zephyr-latest/dts/bindings/i2c/
Datmel,sam-i2c-twim.yaml1 # Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
15 When using speeds above standard mode, user may need adjust clock and data
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
22 std-data-slew-lim = <0>;
23 std-data-strength-low = "0.5";
[all …]
/Zephyr-latest/boards/seagate/faze/
Dfaze-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
13 nxp,disable-analog-filter;
21 nxp,i2c-mode;
22 nxp,i2c-filter = "slow";
23 nxp,disable-analog-filter;
31 nxp,i2c-mode;
32 nxp,i2c-filter = "fast";
33 nxp,disable-analog-filter;
41 drive-open-drain;
[all …]
/Zephyr-latest/soc/atmel/sam/common/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
13 Says y if you want to use external 32 kHz crystal oscillator to drive
15 crystal needs to stabilize after power-up.
24 The main clock is being used to drive the PLL, and thus driving the
27 Says y if you want to use external crystal oscillator to drive the
29 crystal needs to stabilize after power-up.
80 bool "CPU goes to Wait mode instead of Sleep mode"
85 achieve this, make CPU go to Wait mode instead of Sleep mode while
91 At reset ERASE pin is configured in System IO mode. Asserting the
93 option will switch the pin to general IO mode giving control of the
/Zephyr-latest/boards/infineon/cyw920829m2evk_02/
Dcyw920829m2evk_02-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 /* Configure pin control bias mode for uart2 pins */
8 drive-push-pull;
12 input-enable;
16 drive-push-pull;
20 input-enable;

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