1 /*
2  * Copyright (c) 2021 Nordic Semiconductor ASA
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
8 
9 /*
10  * The whole nRF pin configuration information is encoded in a 32-bit bitfield
11  * organized as follows:
12  *
13  * - 31..24: Pin function.
14  * - 19-23:  Reserved.
15  * - 18:     Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
16  * - 17:     Clockpin enable.
17  * - 16:     Pin inversion mode.
18  * - 15:     Pin low power mode.
19  * - 14..11: Pin output drive configuration.
20  * - 10..9:  Pin pull configuration.
21  * - 8..0:   Pin number (combination of port and pin).
22  */
23 
24 /**
25  * @name nRF pin configuration bit field positions and masks.
26  * @{
27  */
28 
29 /** Position of the function field. */
30 #define NRF_FUN_POS 24U
31 /** Mask for the function field. */
32 #define NRF_FUN_MSK 0xFFU
33 /** Position of the GPD FAST ACTIVE1 */
34 #define NRF_GPD_FAST_ACTIVE1_POS 18U
35 /** Mask for the GPD FAST ACTIVE1 */
36 #define NRF_GPD_FAST_ACTIVE1_MSK 0x1U
37 /** Position of the clockpin enable field. */
38 #define NRF_CLOCKPIN_ENABLE_POS 17U
39 /** Mask for the clockpin enable field. */
40 #define NRF_CLOCKPIN_ENABLE_MSK 0x1U
41 /** Position of the invert field. */
42 #define NRF_INVERT_POS 16U
43 /** Mask for the invert field. */
44 #define NRF_INVERT_MSK 0x1U
45 /** Position of the low power field. */
46 #define NRF_LP_POS 15U
47 /** Mask for the low power field. */
48 #define NRF_LP_MSK 0x1U
49 /** Position of the drive configuration field. */
50 #define NRF_DRIVE_POS 11U
51 /** Mask for the drive configuration field. */
52 #define NRF_DRIVE_MSK 0xFU
53 /** Position of the pull configuration field. */
54 #define NRF_PULL_POS 9U
55 /** Mask for the pull configuration field. */
56 #define NRF_PULL_MSK 0x3U
57 /** Position of the pin field. */
58 #define NRF_PIN_POS 0U
59 /** Mask for the pin field. */
60 #define NRF_PIN_MSK 0x1FFU
61 
62 /** @} */
63 
64 /**
65  * @name nRF pinctrl pin functions.
66  * @{
67  */
68 
69 /** UART TX */
70 #define NRF_FUN_UART_TX 0U
71 /** UART RX */
72 #define NRF_FUN_UART_RX 1U
73 /** UART RTS */
74 #define NRF_FUN_UART_RTS 2U
75 /** UART CTS */
76 #define NRF_FUN_UART_CTS 3U
77 /** SPI master SCK */
78 #define NRF_FUN_SPIM_SCK 4U
79 /** SPI master MOSI */
80 #define NRF_FUN_SPIM_MOSI 5U
81 /** SPI master MISO */
82 #define NRF_FUN_SPIM_MISO 6U
83 /** SPI slave SCK */
84 #define NRF_FUN_SPIS_SCK 7U
85 /** SPI slave MOSI */
86 #define NRF_FUN_SPIS_MOSI 8U
87 /** SPI slave MISO */
88 #define NRF_FUN_SPIS_MISO 9U
89 /** SPI slave CSN */
90 #define NRF_FUN_SPIS_CSN 10U
91 /** TWI master SCL */
92 #define NRF_FUN_TWIM_SCL 11U
93 /** TWI master SDA */
94 #define NRF_FUN_TWIM_SDA 12U
95 /** I2S SCK in master mode */
96 #define NRF_FUN_I2S_SCK_M 13U
97 /** I2S SCK in slave mode */
98 #define NRF_FUN_I2S_SCK_S 14U
99 /** I2S LRCK in master mode */
100 #define NRF_FUN_I2S_LRCK_M 15U
101 /** I2S LRCK in slave mode */
102 #define NRF_FUN_I2S_LRCK_S 16U
103 /** I2S SDIN */
104 #define NRF_FUN_I2S_SDIN 17U
105 /** I2S SDOUT */
106 #define NRF_FUN_I2S_SDOUT 18U
107 /** I2S MCK */
108 #define NRF_FUN_I2S_MCK 19U
109 /** PDM CLK */
110 #define NRF_FUN_PDM_CLK 20U
111 /** PDM DIN */
112 #define NRF_FUN_PDM_DIN 21U
113 /** PWM OUT0 */
114 #define NRF_FUN_PWM_OUT0 22U
115 /** PWM OUT1 */
116 #define NRF_FUN_PWM_OUT1 23U
117 /** PWM OUT2 */
118 #define NRF_FUN_PWM_OUT2 24U
119 /** PWM OUT3 */
120 #define NRF_FUN_PWM_OUT3 25U
121 /** QDEC A */
122 #define NRF_FUN_QDEC_A 26U
123 /** QDEC B */
124 #define NRF_FUN_QDEC_B 27U
125 /** QDEC LED */
126 #define NRF_FUN_QDEC_LED 28U
127 /** QSPI SCK */
128 #define NRF_FUN_QSPI_SCK 29U
129 /** QSPI CSN */
130 #define NRF_FUN_QSPI_CSN 30U
131 /** QSPI IO0 */
132 #define NRF_FUN_QSPI_IO0 31U
133 /** QSPI IO1 */
134 #define NRF_FUN_QSPI_IO1 32U
135 /** QSPI IO2 */
136 #define NRF_FUN_QSPI_IO2 33U
137 /** QSPI IO3 */
138 #define NRF_FUN_QSPI_IO3 34U
139 /** EXMIF CK */
140 #define NRF_FUN_EXMIF_CK 35U
141 /** EXMIF DQ0 */
142 #define NRF_FUN_EXMIF_DQ0 36U
143 /** EXMIF DQ1 */
144 #define NRF_FUN_EXMIF_DQ1 37U
145 /** EXMIF DQ2 */
146 #define NRF_FUN_EXMIF_DQ2 38U
147 /** EXMIF DQ3 */
148 #define NRF_FUN_EXMIF_DQ3 39U
149 /** EXMIF DQ4 */
150 #define NRF_FUN_EXMIF_DQ4 40U
151 /** EXMIF DQ5 */
152 #define NRF_FUN_EXMIF_DQ5 41U
153 /** EXMIF DQ6 */
154 #define NRF_FUN_EXMIF_DQ6 42U
155 /** EXMIF DQ7 */
156 #define NRF_FUN_EXMIF_DQ7 43U
157 /** EXMIF CS0 */
158 #define NRF_FUN_EXMIF_CS0 44U
159 /** EXMIF CS1 */
160 #define NRF_FUN_EXMIF_CS1 45U
161 /** CAN TX */
162 #define NRF_FUN_CAN_TX 46U
163 /** CAN RX */
164 #define NRF_FUN_CAN_RX 47U
165 /** TWIS SCL */
166 #define NRF_FUN_TWIS_SCL 48U
167 /** TWIS SDA */
168 #define NRF_FUN_TWIS_SDA 49U
169 
170 /** @} */
171 
172 /**
173  * @name nRF pinctrl output drive.
174  * @{
175  */
176 
177 /** Standard '0', standard '1'. */
178 #define NRF_DRIVE_S0S1 0U
179 /** High drive '0', standard '1'. */
180 #define NRF_DRIVE_H0S1 1U
181 /** Standard '0', high drive '1'. */
182 #define NRF_DRIVE_S0H1 2U
183 /** High drive '0', high drive '1'. */
184 #define NRF_DRIVE_H0H1 3U
185 /** Disconnect '0' standard '1'. */
186 #define NRF_DRIVE_D0S1 4U
187 /** Disconnect '0', high drive '1'. */
188 #define NRF_DRIVE_D0H1 5U
189 /** Standard '0', disconnect '1'. */
190 #define NRF_DRIVE_S0D1 6U
191 /** High drive '0', disconnect '1'. */
192 #define NRF_DRIVE_H0D1 7U
193 /** Extra high drive '0', extra high drive '1'. */
194 #define NRF_DRIVE_E0E1 8U
195 
196 /** @} */
197 
198 /**
199  * @name nRF pinctrl pull-up/down.
200  * @note Values match nrf_gpio_pin_pull_t constants.
201  * @{
202  */
203 
204 /** Pull-up disabled. */
205 #define NRF_PULL_NONE 0U
206 /** Pull-down enabled. */
207 #define NRF_PULL_DOWN 1U
208 /** Pull-up enabled. */
209 #define NRF_PULL_UP 3U
210 
211 /** @} */
212 
213 /**
214  * @name nRF pinctrl low power mode.
215  * @{
216  */
217 
218 /** Input. */
219 #define NRF_LP_DISABLE 0U
220 /** Output. */
221 #define NRF_LP_ENABLE 1U
222 
223 /** @} */
224 
225 /**
226  * @name nRF pinctrl helpers to indicate disconnected pins.
227  * @{
228  */
229 
230 /** Indicates that a pin is disconnected */
231 #define NRF_PIN_DISCONNECTED NRF_PIN_MSK
232 
233 /** @} */
234 
235 /**
236  * @brief Utility macro to build nRF psels property entry.
237  *
238  * @param fun Pin function configuration (see NRF_FUNC_{name} macros).
239  * @param port Port (0 or 15).
240  * @param pin Pin (0..31).
241  */
242 #define NRF_PSEL(fun, port, pin)						       \
243 	((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) |		       \
244 	 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
245 
246 /**
247  * @brief Utility macro to build nRF psels property entry when a pin is disconnected.
248  *
249  * This can be useful in situations where code running before Zephyr, e.g. a bootloader
250  * configures pins that later needs to be disconnected.
251  *
252  * @param fun Pin function configuration (see NRF_FUN_{name} macros).
253  */
254 #define NRF_PSEL_DISCONNECTED(fun)						       \
255 	(NRF_PIN_DISCONNECTED |							       \
256 	 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
257 
258 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */
259