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/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
[all …]
/Zephyr-latest/dts/bindings/ospi/
Dst,stm32-ospi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
16 dma-names = "tx_rx";
21 compatible: "st,stm32-ospi"
23 include: [base.yaml, pinctrl-device.yaml]
34 pinctrl-0:
37 pinctrl-names:
40 clock-names:
45 Optional DMA channel specifier, required for DMA transactions.
50 - &dma1: dma controller phandle
[all …]
/Zephyr-latest/dts/bindings/dma/
Dsilabs,si32-dma.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: Si32 DMA controller
7 compatible: "silabs,si32-dma"
9 include: dma-controller.yaml
18 dma-channels:
21 Limiting the number of enabled channels saves RAM.
23 "#dma-cells":
26 dma-cells:
27 - channel
28 - high-prio
[all …]
Dst,stm32-dma-v2bis.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
7 This DMA controller includes several channels with different requests.
8 All the requests ar ORed before entering the DMA, so that only one request
9 must be enabled at a time.
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
[all …]
/Zephyr-latest/drivers/dma/
DKconfig.dw_axi_dmac1 # DesignWare DMA configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "DesignWare AXI DMA driver"
12 DesignWare AXI DMA driver.
27 This flag can be enabled if hardware support Linked List multi-block transfer
DKconfig.dw_common1 # DesignWare DMA common configuration options
4 # SPDX-License-Identifier: Apache-2.0
24 When not enabled the driver will still perform scatter gather but using software
31 Rather than immediately stopping a DMA channel the channel is suspended
46 Channel count for designware DMA instances.
Ddma_si32.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/dma.h>
32 "There is just one DMA controller");
34 #define CHANNEL_COUNT DT_INST_PROP(0, dma_channels) /* number of used/enabled DMA channels */
70 result = -EIO; in dma_si32_isr_handler()
73 __ASSERT(channel_descriptor->CONFIG.TMD == 0, "Result of success: TMD set to zero"); in dma_si32_isr_handler()
74 __ASSERT(channel_descriptor->CONFIG.NCOUNT == 0, in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
101 __ASSERT(SI32_DMACTRL_0 == SI32_DMACTRL_0, "There is only one DMA controller"); in dma_si32_init()
105 /* Route clock to the DMA controller */ in dma_si32_init()
[all …]
Ddma_max32.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/dma.h>
36 /* mxc_dma_priority_t is limited to values 0-3 */ in max32_dma_ch_prio_valid()
38 LOG_ERR("Invalid DMA priority - must be type mxc_dma_priority_t (0-3)"); in max32_dma_ch_prio_valid()
54 LOG_ERR("Invalid DMA width - must be byte (1), halfword (2) or word (4)"); in max32_dma_width()
55 return -EINVAL; in max32_dma_width()
67 LOG_ERR("Invalid DMA address adjust - must be NO_CHANGE (0) or INCREMENT (1)"); in max32_dma_addr_adj()
72 static inline int max32_dma_ch_index(mxc_dma_regs_t *dma, uint8_t ch) in max32_dma_ch_index() argument
74 return (ch + MXC_DMA_GET_IDX(dma) * (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES)); in max32_dma_ch_index()
80 const struct max32_dma_config *cfg = dev->config; in max32_dma_config()
[all …]
Ddma_sam_xdmac.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/drivers/dma.h>
31 /* DMA channel configuration */
53 const struct sam_xdmac_dev_cfg *const dev_cfg = dev->config; in sam_xdmac_isr()
54 struct sam_xdmac_dev_data *const dev_data = dev->data; in sam_xdmac_isr()
56 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_isr()
62 isr_status = xdmac->XDMAC_GIS; in sam_xdmac_isr()
69 channel_cfg = &dev_data->dma_channels[channel]; in sam_xdmac_isr()
72 err = xdmac->XDMAC_CHID[channel].XDMAC_CIS & XDMAC_INT_ERR; in sam_xdmac_isr()
75 if (channel_cfg->callback) { in sam_xdmac_isr()
[all …]
/Zephyr-latest/doc/hardware/cache/
Dguide.rst15 The information here assumes that the architecture-specific MPU support is
16 enabled. See the architecture-specific documentation for details.
23 with external hardware like DMA controllers or foreign CPUs running a
30 of this, data moved into and out of memory by DMA engines will be stale in the
32 moving data using DMA and the processor doesn't see the data you expect, cache
40 coherence is more important than performance, such as when using DMA with SPI.
45 ---------------------------------
52 * :kconfig:option:`CONFIG_DCACHE`: DCACHE control enabled in Zephyr.
54 * :kconfig:option:`CONFIG_CACHE_MANAGEMENT`: cache API enabled.
59 -------------------------------------
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/Zephyr-latest/boards/nxp/mimxrt1160_evk/
Dmimxrt1160_evk_mimxrt1166_cm4.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 model = "NXP MIMXRT1160-EVK board";
18 * Note: when using DMA, the SRAM region must be set to
20 * sram region is changed and DMA is in use, you will
25 zephyr,shell-uart = &lpuart1;
26 zephyr,flash-controller = &is25wp128;
28 nxp,m4-partition = &slot1_partition;
34 /* Winbond W9825G6KH-5I */
43 current-speed = <115200>;
[all …]
/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
37 description: Enable SPI DMA support
[all …]
Dinfineon,xmc4xxx-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "infineon,xmc4xxx-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
14 miso-src:
23 - "DX0A"
24 - "DX0B"
25 - "DX0C"
26 - "DX0D"
27 - "DX0E"
28 - "DX0F"
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dst,stm32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
14 dma-names = "tx_rx";
19 compatible: "st,stm32-qspi"
21 include: [base.yaml, pinctrl-device.yaml]
32 pinctrl-0:
35 pinctrl-names:
40 Optional DMA channel specifier. If DMA should be used, specifier should
41 hold a phandle reference to the dma controller (not the DMAMUX even if present),
43 (depending on the type of DMA: 'features' is optional)
[all …]
/Zephyr-latest/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk_mimxrt1176_cm4.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 model = "NXP MIMXRT1170-EVK board";
18 * Note: when using DMA, the SRAM region must be set to
20 * sram region is changed and DMA is in use, you will
25 zephyr,shell-uart = &lpuart1;
27 zephyr,flash-controller = &is25wp128;
29 nxp,m4-partition = &slot1_partition;
34 /* Winbond W9825G6KH-5I */
43 current-speed = <115200>;
[all …]
/Zephyr-latest/drivers/i2s/
DKconfig.sam_ssc4 # SPDX-License-Identifier: Apache-2.0
11 select DMA
27 bool "RF pin enabled"
30 If enabled RF signal is connected to RF pin. It will be configured as
38 bool "RK pin enabled"
41 If enabled RK signal is connected to RK pin. It will be configured as
/Zephyr-latest/drivers/audio/
Ddmic_mcux.c7 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
27 const struct device *dma; member
57 * - DMIC DIVHFCLK is set to 0x0 (divide by 1) in dmic_mcux_get_osr()
58 * - DMIC PHY_HALF is set to 0x0 (standard sample rate) in dmic_mcux_get_osr()
74 dmic_parse_channel_map(drv_data->chan_map_lo, in dmic_mcux_hw_chan()
75 drv_data->chan_map_hi, in dmic_mcux_hw_chan()
88 /* PDM channel 0 must always be enabled, as the RM states: in dmic_mcux_activate_channels()
95 for (uint8_t chan = 0; chan < drv_data->act_num_chan; chan++) { in dmic_mcux_activate_channels()
101 DMIC_EnableChannnel(drv_data->base_address, mask); in dmic_mcux_activate_channels()
[all …]
/Zephyr-latest/dts/bindings/usb/
Drenesas,smartbond-usbd.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-usbd"
8 include: usb-ep.yaml
11 dma-min-transfer-size:
14 Minimum transfer size required to engage DMA.
16 ep-out-buf-size:
20 Buffer size for OUT end points 0-3.
22 fifo-read-threshold:
26 FIFO warning interrupt is enabled to allow read incoming data
40 iso-out-mps:
/Zephyr-latest/dts/bindings/i2s/
Dst,stm32-i2s-common.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [i2s-controller.yaml, pinctrl-device.yaml]
18 dma-names:
21 pinctrl-0:
24 pinctrl-names:
27 mck-enabled:
31 An mck pin must be listed within pinctrl-0 when enabling this property.
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h7 * SPDX-License-Identifier: Apache-2.0
332 #define XGMAC_RXQxEN_DCB (2u) /* RX queue enabled for Data Center Bridging or Generic */
404 * @brief TX DMA memory area buffer descriptor ring management structure.
406 * The DMA memory area buffer descriptor ring management structure
429 * @brief RX DMA memory area buffer descriptor ring management structure.
431 * The DMA memory area buffer descriptor ring management structure
467 * the EDMA starts pre-fetching the TxDMA descriptors
471 * the EDMA starts pre-fetching the RxDMA descriptors
492 /* Address-Aligned Beats. When this bit is set to 1, the AXI master performs
493 * address-aligned burst transfers on Read and Write channels
[all …]
/Zephyr-latest/drivers/serial/
DKconfig.xmc4xxx4 # SPDX-License-Identifier: Apache-2.0
13 select DMA if UART_ASYNC_API
24 When this option is enabled, an interrupt will continue to trigger
/Zephyr-latest/drivers/display/
Ddisplay_renesas_lcdc.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/dma.h>
68 /* DMA device */
69 const struct device *dma; member
70 /* DMA configuration structures */
73 /* DMA memory transfer synchronization token */
75 /* Granted DMA channel used for memory transfers */
104 if (atomic_test_and_set_bit(data->pm_policy_state_flag, 0) == 0) { in lcdc_smartbond_pm_policy_state_lock_get()
117 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, 0) == 1) { in lcdc_smartbond_pm_policy_state_lock_put()
143 const struct display_smartbond_config *config = dev->config; in display_smartbond_configure()
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f091.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32f091", "st,stm32f0", "simple-bus";
14 * USARTs 3-8 share the same IRQ on stm32f091xx devices. This
16 * these may be enabled at a time. Enabling more than one will
20 compatible = "st,stm32-usart", "st,stm32-uart";
29 compatible = "st,stm32-usart", "st,stm32-uart";
38 compatible = "st,stm32-usart", "st,stm32-uart";
47 compatible = "st,stm32-usart", "st,stm32-uart";
56 compatible = "st,stm32-bxcan";
63 dma2: dma@40020400 {
[all …]
/Zephyr-latest/dts/bindings/display/
Dnxp,imx-elcdif.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-elcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 data-bus-width:
19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
[all …]
/Zephyr-latest/drivers/usb/common/nrf_usbd_common/
Dnrf_usbd_common_errata.h2 * Copyright (c) 2016 - 2023, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
19 * @brief The constant that informs if errata should be enabled at all.
38 /* Errata: USB cannot be enabled. **/
44 /* Errata: USBD cannot receive tasks during DMA. **/

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