1# DesignWare DMA configuration options
2
3# Copyright (c) 2023 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config DMA_DW_AXI
7	bool "DesignWare AXI DMA driver"
8	default y
9	depends on DT_HAS_SNPS_DESIGNWARE_DMA_AXI_ENABLED
10	imply DMA_64BIT
11	help
12	  DesignWare AXI DMA driver.
13
14if DMA_DW_AXI
15
16config DMA_DW_AXI_MAX_DESC
17	int "allocate number of lli descriptor"
18	default 10
19	help
20	  creates number of descriptor per channel in a statically allocated pool.
21	  Each channel has its own dedicated pool.
22
23config DMA_DW_AXI_LLI_SUPPORT
24	bool "hardware supports linked list multi block transfer"
25	default y
26	help
27	  This flag can be enabled if hardware support Linked List multi-block transfer
28
29config DMA_CHANNEL_STATUS_TIMEOUT
30	int "Channel status timeout"
31	default 1000
32	help
33	  Max timeout to abort or disable the channel
34
35config DMA_DW_AXI_MAX_BURST_TXN_LEN
36	int "max burst transaction length"
37	default 8
38	help
39	  set max number of source and destination data units supported
40
41config DMA_DW_AXI_DATA_WIDTH
42	int "data bus width"
43	default 64
44	help
45	  update this flag to change the axi master interface data width
46
47config DMA_DW_AXI_MAX_BLOCK_TS
48	int "max block size"
49	default 32767
50	help
51	  update this config to set maximum value of block size
52
53endif # DMA_DW_AXI
54