Lines Matching +full:dma +full:- +full:enabled
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/dma.h>
36 /* mxc_dma_priority_t is limited to values 0-3 */ in max32_dma_ch_prio_valid()
38 LOG_ERR("Invalid DMA priority - must be type mxc_dma_priority_t (0-3)"); in max32_dma_ch_prio_valid()
54 LOG_ERR("Invalid DMA width - must be byte (1), halfword (2) or word (4)"); in max32_dma_width()
55 return -EINVAL; in max32_dma_width()
67 LOG_ERR("Invalid DMA address adjust - must be NO_CHANGE (0) or INCREMENT (1)"); in max32_dma_addr_adj()
72 static inline int max32_dma_ch_index(mxc_dma_regs_t *dma, uint8_t ch) in max32_dma_ch_index() argument
74 return (ch + MXC_DMA_GET_IDX(dma) * (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES)); in max32_dma_ch_index()
80 const struct max32_dma_config *cfg = dev->config; in max32_dma_config()
81 struct max32_dma_data *data = dev->data; in max32_dma_config()
84 if (channel >= cfg->channels) { in max32_dma_config()
85 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_config()
87 return -EINVAL; in max32_dma_config()
90 ch = max32_dma_ch_index(cfg->regs, channel); in max32_dma_config()
92 /* DMA Channel Config */ in max32_dma_config()
96 mxc_dma_cfg.reqsel = config->dma_slot << ADI_MAX32_DMA_CFG_REQ_POS; in max32_dma_config()
97 if (((max32_dma_width(config->source_data_size)) < 0) || in max32_dma_config()
98 ((max32_dma_width(config->dest_data_size)) < 0)) { in max32_dma_config()
99 return -EINVAL; in max32_dma_config()
101 mxc_dma_cfg.srcwd = max32_dma_width(config->source_data_size); in max32_dma_config()
102 mxc_dma_cfg.dstwd = max32_dma_width(config->dest_data_size); in max32_dma_config()
103 mxc_dma_cfg.srcinc_en = max32_dma_addr_adj(config->head_block->source_addr_adj); in max32_dma_config()
104 mxc_dma_cfg.dstinc_en = max32_dma_addr_adj(config->head_block->dest_addr_adj); in max32_dma_config()
106 /* DMA Channel Advanced Config */ in max32_dma_config()
110 if (!max32_dma_ch_prio_valid(config->channel_priority)) { in max32_dma_config()
111 return -EINVAL; in max32_dma_config()
113 mxc_dma_cfg_adv.prio = config->channel_priority; in max32_dma_config()
117 mxc_dma_cfg_adv.burst_size = config->source_burst_length; in max32_dma_config()
119 /* DMA Transfer Config */ in max32_dma_config()
123 txfer.source = (void *)config->head_block->source_address; in max32_dma_config()
124 txfer.dest = (void *)config->head_block->dest_address; in max32_dma_config()
125 txfer.len = config->head_block->block_size; in max32_dma_config()
137 /* Enable interrupts for the DMA peripheral */ in max32_dma_config()
143 /* Enable complete and count-to-zero interrupts for the channel */ in max32_dma_config()
149 data[channel].callback = config->dma_callback; in max32_dma_config()
150 data[channel].cb_data = config->user_data; in max32_dma_config()
151 data[channel].err_cb_dis = config->error_callback_dis; in max32_dma_config()
159 const struct max32_dma_config *cfg = dev->config; in max32_dma_reload()
163 if (channel >= cfg->channels) { in max32_dma_reload()
164 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_reload()
166 return -EINVAL; in max32_dma_reload()
169 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_reload()
172 return -EBUSY; in max32_dma_reload()
184 const struct max32_dma_config *cfg = dev->config; in max32_dma_start()
187 if (channel >= cfg->channels) { in max32_dma_start()
188 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_start()
190 return -EINVAL; in max32_dma_start()
193 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_start()
196 return -EBUSY; in max32_dma_start()
204 const struct max32_dma_config *cfg = dev->config; in max32_dma_stop()
206 if (channel >= cfg->channels) { in max32_dma_stop()
207 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_stop()
209 return -EINVAL; in max32_dma_stop()
212 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_stop()
219 const struct max32_dma_config *cfg = dev->config; in max32_dma_get_status()
224 if (channel >= cfg->channels) { in max32_dma_get_status()
225 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_get_status()
227 return -EINVAL; in max32_dma_get_status()
230 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_get_status()
240 /* Channel is busy if channel status is enabled */ in max32_dma_get_status()
241 stat->busy = (flags & ADI_MAX32_DMA_STATUS_ST) != 0; in max32_dma_get_status()
242 stat->pending_length = txfer.len; in max32_dma_get_status()
249 const struct max32_dma_config *cfg = dev->config; in max32_dma_isr()
250 struct max32_dma_data *data = dev->data; in max32_dma_isr()
251 mxc_dma_regs_t *regs = cfg->regs; in max32_dma_isr()
256 uint8_t channel_base = max32_dma_ch_index(cfg->regs, 0); in max32_dma_isr()
258 for (ch = channel_base, c = 0; c < cfg->channels; ch++, c++) { in max32_dma_isr()
268 status = -EIO; in max32_dma_isr()
274 /* Only call error callback if enabled during DMA config */ in max32_dma_isr()
291 const struct max32_dma_config *cfg = dev->config; in max32_dma_init()
293 if (!device_is_ready(cfg->clock)) { in max32_dma_init()
294 return -ENODEV; in max32_dma_init()
298 ret = clock_control_on(cfg->clock, (clock_control_subsys_t) &(cfg->perclk)); in max32_dma_init()
303 ret = Wrap_MXC_DMA_Init(cfg->regs); in max32_dma_init()
309 for (int i = 0; i < cfg->channels; i++) { in max32_dma_init()
310 ret = Wrap_MXC_DMA_AcquireChannel(cfg->regs); in max32_dma_init()
316 cfg->irq_configure(); in max32_dma_init()
321 static DEVICE_API(dma, max32_dma_driver_api) = {
337 static struct max32_dma_data dma##inst##_data[DT_INST_PROP(inst, dma_channels)]; \
342 static const struct max32_dma_config dma##inst##_cfg = { \
350 DEVICE_DT_INST_DEFINE(inst, &max32_dma_init, NULL, &dma##inst##_data, &dma##inst##_cfg, \