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/Zephyr-latest/dts/arm/st/f1/
Dstm32f107.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32f107", "st,stm32f1", "simple-bus";
13 dma2: dma@40020400 {
14 compatible = "st,stm32-dma-v2bis";
15 #dma-cells = <2>;
23 compatible = "st,stm32-ethernet";
26 clock-names = "stmmaceth", "mac-clk-tx",
27 "mac-clk-rx";
/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
37 description: Enable SPI DMA support
[all …]
/Zephyr-latest/drivers/sdhc/
Drcar_mmc_registers.h4 * SPDX-License-Identifier: Apache-2.0
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
108 #define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
109 #define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
110 #define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
111 #define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
112 #define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
113 #define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
114 #define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
115 #define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S6x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <arm/armv8-m.dtsi>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 zephyr,flash-controller = &iap;
[all …]
Dnxp_mcxn23x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
[all …]
Dnxp_mcxn94x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
[all …]
Dnxp_rt5xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
Dnxp_s32z27x_r52.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-r52";
26 compatible = "arm,cortex-r52";
[all …]
Dnxp_ke1xf.dtsi2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ftfe;
24 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/mmc/
Dst,stm32-sdmmc.yaml3 compatible: "st,stm32-sdmmc"
5 include: [mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 cd-gpios:
24 type: phandle-array
27 pwr-gpios:
28 type: phandle-array
31 bus-width:
38 - 1
[all …]
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/dts/arm/silabs/
Dsim3u.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
13 zephyr,flash-controller = &flash;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m3";
23 clock-frequency = <20000000>;
29 compatible = "mmio-sram";
33 compatible = "silabs,si32-pinctrl";
[all …]
/Zephyr-latest/dts/bindings/ospi/
Dst,stm32-ospi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
16 dma-names = "tx_rx";
21 compatible: "st,stm32-ospi"
23 include: [base.yaml, pinctrl-device.yaml]
34 pinctrl-0:
37 pinctrl-names:
40 clock-names:
45 Optional DMA channel specifier, required for DMA transactions.
50 - &dma1: dma controller phandle
[all …]
/Zephyr-latest/boards/seeed/xiao_esp32s3/
Dxiao_esp32s3_procpu_sense.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "seeed,xiao-esp32s3";
22 clock-frequency = <I2C_BITRATE_STANDARD>;
23 pinctrl-0 = <&i2c1_default>;
24 pinctrl-names = "default";
30 clock-rate-control = <0x80>;
33 remote-endpoint-label = "dvp_ep_in";
39 &dma {
45 cam-clk = <10000000>;
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
[all …]
Drp2350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
12 #include <zephyr/dt-bindings/reset/rp2350_reset.h>
21 die-temp0 = &die_temp;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/st/wb/
Dstm32wb.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dfrdm_k64f.overlay2 * SPDX-License-Identifier: Apache-2.0
9 io-channels = <&adc0 14>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 clk-source = <0>;
17 hw-trigger-src = <4>;
18 continuous-convert;
19 high-speed;
20 periodic-trigger;
27 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
[all …]
Dfrdm_k82f.overlay2 * SPDX-License-Identifier: Apache-2.0
9 io-channels = <&adc0 15>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 clk-source = <0>;
17 hw-trigger-src = <4>;
18 continuous-convert;
19 high-speed;
20 periodic-trigger;
27 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
[all …]
/Zephyr-latest/dts/arm/st/c0/
Dstm32c0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/dma/stm32_dma.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h5.dtsi2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
[all …]
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
11 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
12 #include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 zephyr,flash-controller = &flash;
24 #address-cells = <1>;
[all …]
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnucleo_h743zi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Set div-q to get test clk freq into acceptable SPI freq range */
9 /delete-property/ div-q;
10 div-q = <8>;
14 zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
20 dma-names = "tx", "rx";
22 compatible = "test-spi-loopback-slow";
24 spi-max-frequency = <500000>;
27 compatible = "test-spi-loopback-fast";
29 spi-max-frequency = <16000000>;
Dnucleo_h745zi_q_stm32h745xx_m4.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Set div-q to get test clk freq into acceptable SPI freq range */
9 /delete-property/ div-q;
10 div-q = <8>;
14 zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
20 dma-names = "tx", "rx";
22 compatible = "test-spi-loopback-slow";
24 spi-max-frequency = <500000>;
27 compatible = "test-spi-loopback-fast";
29 spi-max-frequency = <16000000>;

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