Lines Matching +full:dma +full:- +full:clk
4 * SPDX-License-Identifier: Apache-2.0
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
108 #define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
109 #define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
110 #define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
111 #define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
112 #define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
113 #define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
114 #define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
115 #define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
116 #define RCAR_MMC_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
117 #define RCAR_MMC_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
149 /* The DMA mode enable register enables the DMA transfer. */
151 #define RCAR_MMC_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
177 #define RCAR_MMC_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
182 #define RCAR_MMC_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
183 #define RCAR_MMC_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
184 #define RCAR_MMC_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */