1/*
2 * Copyright (c) 2024 GARDENA GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <freq.h>
10
11/ {
12	chosen {
13		zephyr,flash-controller = &flash;
14	};
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-m3";
22			device_type = "cpu";
23			clock-frequency = <20000000>;
24			reg = <0>;
25		};
26	};
27
28	sram0: memory@20000000 {
29		compatible = "mmio-sram";
30	};
31
32	pinctrl: pinctrl {
33		compatible = "silabs,si32-pinctrl";
34		status = "okay";
35	};
36
37	clocks {
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		pll0: pll0@4003b000 {
42			compatible = "silabs,si32-pll";
43			#clock-cells = <0>;
44			reg = <0x4003b000>;
45			status = "disabled";
46		};
47
48		clk_ahb: clk-ahb {
49			compatible = "silabs,si32-ahb";
50			#clock-cells = <0>;
51			status = "disabled";
52		};
53
54		clk_apb: clk-apb {
55			compatible = "silabs,si32-apb";
56			#clock-cells = <0>;
57			divider = <1>;
58			clocks = <&clk_ahb>;
59			status = "disabled";
60		};
61	};
62
63	soc {
64		dma: dma-controller@40036000 {
65			compatible = "silabs,si32-dma";
66			reg = <0x40036000 0x1000>;
67			interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
68				     <8 0>, <9 0>, <10 0>, <11 0>,
69				     <12 0>, <13 0>, <14 0>, <15 0>,
70				     <16 0>, <17 0>, <18 0>, <19 0>;
71			dma-channels = <16>;
72			#dma-cells = <3>;
73			status = "disabled";
74		};
75
76		crypto: crypto@40027000 {
77			compatible = "silabs,si32-aes";
78			reg = <0x40027000 0x1000>;
79			interrupts = <42 0>;
80			dmas = <&dma 5 0 0>,
81			       <&dma 6 0 0>,
82			       <&dma 7 0 0>;
83			dma-names = "tx", "rx", "xor";
84			status = "disabled";
85		};
86
87		flash: flash-controller@4002e000 {
88			compatible = "silabs,si32-flash-controller";
89			reg = <0x4002e000 0x1000>;
90
91			#address-cells = <1>;
92			#size-cells = <1>;
93
94			flash0: flash@0 {
95				compatible = "soc-nv-flash";
96				write-block-size = <2>;
97			};
98		};
99
100		usart0: usart@40000000 {
101			compatible = "silabs,si32-usart";
102			reg = <0x40000000 0x1000>;
103			interrupts = <27 0>;
104			clocks = <&clk_apb>;
105			status = "disabled";
106		};
107
108		usart1: usart@40001000 {
109			compatible = "silabs,si32-usart";
110			reg = <0x40001000 0x1000>;
111			interrupts = <28 0>;
112			clocks = <&clk_apb>;
113			status = "disabled";
114		};
115
116		gpio0: gpio@4002a0a0 {
117			compatible = "silabs,si32-gpio";
118			gpio-controller;
119			#gpio-cells = <2>;
120			reg = <0x4002a0a0 0xa0>;
121		};
122
123		gpio1: gpio@4002a140 {
124			compatible = "silabs,si32-gpio";
125			gpio-controller;
126			#gpio-cells = <2>;
127			reg = <0x4002a140 0xa0>;
128		};
129
130		gpio2: gpio@4002a1e0 {
131			compatible = "silabs,si32-gpio";
132			gpio-controller;
133			#gpio-cells = <2>;
134			reg = <0x4002a1e0 0xc0>;
135		};
136
137		gpio3: gpio@4002a320 {
138			compatible = "silabs,si32-gpio";
139			gpio-controller;
140			#gpio-cells = <2>;
141			reg = <0x4002a320 0xa0>;
142		};
143	};
144};
145
146&nvic {
147	arm,num-irq-priority-bits = <4>;
148};
149