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/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-xspi-nor.yaml1 # Copyright (c) 2021 - 2024 STMicroelectronics
2 # SPDX-License-Identifier: Apache-2.0
7 Representation of a serial flash on a xspi bus:
9 mx25lm51245: xspi-nor-flash@70000000 {
10 compatible = "st,stm32-xspi-nor";
12 data-mode = <XSPI_OCTO_MODE>; /* access on 8 data lines */
13 data-rate = <XSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-xspi-nor"
21 - name: st,stm32-ospi-nor.yaml
[all …]
Dst,stm32-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Representation of a serial flash on a quadspi bus:
9 mx25r6435f: qspi-nor-flash@90000000 {
10 compatible = "st,stm32-qspi-nor";
12 qspi-max-frequency = <80000000>;
13 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
14 reset-gpios-duration = <1>;
15 spi-bus-width = <4>;
19 compatible: "st,stm32-qspi-nor"
21 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
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Dst,stm32-ospi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Representation of a serial flash on a octospi bus:
9 mx25lm51245: ospi-nor-flash@70000000 {
10 compatible = "st,stm32-ospi-nor";
12 data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-ospi-nor"
20 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
22 on-bus: ospi
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/Zephyr-latest/dts/bindings/video/
Dvideo-interfaces.yaml2 # SPDX-License-Identifier: Apache-2.0
8 data receivers, video data processors, etc. Data interfaces on these devices are
13 bus, an 'endpoint' child node must be provided for each of them. If more than one
16 scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
19 specify #address-cells, #size-cells properties independently for the 'port' and
25 #address-cells = <1>;
26 #size-cells = <0>;
37 Two 'endpoint' nodes must be linked with each other via their 'remote-endpoint'
39 references are currently not possible. A 'remote-endpoint-label' string is used
40 instead to be able to specify, at least, the label of the peer remote-endpoint.
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Dst,stm32-dcmi.yaml4 # SPDX-License-Identifier: Apache-2.0
14 pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
17 pinctrl-names = "default";
18 bus-width = <8>;
19 hsync-active = <0>;
20 vsync-active = <0>;
21 pixelclk-active = <1>;
22 capture-rate = <1>;
29 remote-endpoint = <&ov2640_ep_out>;
34 compatible: "st,stm32-dcmi"
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/Zephyr-latest/dts/bindings/display/
Dnxp,imx-elcdif.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-elcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 data-bus-width:
19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
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Dnxp,dcnano-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dcnano-lcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 backlight-gpios:
18 type: phandle-array
23 data-bus-width:
25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
29 - "16-bit-config3" # 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX
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/Zephyr-latest/drivers/display/
Dssd1306.c4 * SPDX-License-Identifier: Apache-2.0
41 union ssd1306_bus bus; member
48 uint16_t width; member
71 const struct ssd1306_config *config = dev->config; in ssd1306_bus_ready_i2c()
73 return i2c_is_ready_dt(&config->bus.i2c); in ssd1306_bus_ready_i2c()
78 const struct ssd1306_config *config = dev->config; in ssd1306_write_bus_i2c()
80 return i2c_burst_write_dt(&config->bus.i2c, in ssd1306_write_bus_i2c()
88 const struct ssd1306_config *config = dev->config; in ssd1306_bus_name_i2c()
90 return config->bus.i2c.bus->name; in ssd1306_bus_name_i2c()
98 const struct ssd1306_config *config = dev->config; in ssd1306_bus_ready_spi()
[all …]
Dls0xx.c4 * SPDX-License-Identifier: Apache-2.0
25 * -> high/1 means white, low/0 means black
26 * -> Display expects LSB first
29 #define LS0XX_PANEL_WIDTH DT_INST_PROP(0, width)
35 * +-------------------+-------------------+----------------+
36 * | line num (8 bits) | data (WIDTH bits) | dummy (8 bits) |
37 * +-------------------+-------------------+----------------+
46 struct spi_dt_spec bus; member
62 gpio_pin_toggle_dt(&config->extcomin_gpio); in ls0xx_vcom_toggle()
64 gpio_pin_toggle_dt(&config->extcomin_gpio); in ls0xx_vcom_toggle()
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Ddisplay_stm32_ltdc.c2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
6 * SPDX-License-Identifier: Apache-2.0
36 /* Data enable pulse polarity */
72 uint32_t width; member
85 struct display_stm32_ltdc_data *data = dev->data; in stm32_ltdc_global_isr() local
87 if (__HAL_LTDC_GET_FLAG(&data->hltdc, LTDC_FLAG_LI) && in stm32_ltdc_global_isr()
88 __HAL_LTDC_GET_IT_SOURCE(&data->hltdc, LTDC_IT_LI)) { in stm32_ltdc_global_isr()
89 if (data->front_buf != data->pend_buf) { in stm32_ltdc_global_isr()
90 data->front_buf = data->pend_buf; in stm32_ltdc_global_isr()
92 LTDC_LAYER(&data->hltdc, LTDC_LAYER_1)->CFBAR = (uint32_t)data->front_buf; in stm32_ltdc_global_isr()
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/Zephyr-latest/drivers/dma/
DKconfig.dw_axi_dmac4 # SPDX-License-Identifier: Apache-2.0
27 This flag can be enabled if hardware support Linked List multi-block transfer
39 set max number of source and destination data units supported
42 int "data bus width"
45 update this flag to change the axi master interface data width
Ddma_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
45 DMA->DMA_REQ_MUX_REG = \
46 (DMA->DMA_REQ_MUX_REG & ~(0xf << DMA_MUX_SHIFT((_idx)))) | \
50 ((DMA->DMA_REQ_MUX_REG >> DMA_MUX_SHIFT((_idx))) & 0xf)
59 * when two or more channels request the bus at the same time. For channels of same priority an
93 * DMA bus width indicating how many bytes are retrived/written per transfer.
94 * Note that the bus width is the same for the source and destination.
155 /* Should be the first member of the driver data */
160 /* User callbacks and data to be stored per channel */
173 if (DMA_CTRL_REG_GET_FIELD(DMA_ON, regs->DMA_CTRL_REG)) { in dma_smartbond_is_dma_active()
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/Zephyr-latest/dts/bindings/sdhc/
Despressif,esp32-sdhc-slot.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-sdhc-slot"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 bus-width:
23 - 1
24 - 4
26 description: SD bus width in bits
28 clk-pin:
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/Zephyr-latest/subsys/sd/
Dsdmmc.c4 * SPDX-License-Identifier: Apache-2.0
25 scr->flags = 0U; in sdmmc_decode_scr()
26 scr->scr_structure = (uint8_t)((raw_scr[0U] & 0xF0000000U) >> 28U); in sdmmc_decode_scr()
27 scr->sd_spec = (uint8_t)((raw_scr[0U] & 0xF000000U) >> 24U); in sdmmc_decode_scr()
29 scr->flags |= SD_SCR_DATA_STATUS_AFTER_ERASE; in sdmmc_decode_scr()
31 scr->sd_sec = (uint8_t)((raw_scr[0U] & 0x700000U) >> 20U); in sdmmc_decode_scr()
32 scr->sd_width = (uint8_t)((raw_scr[0U] & 0xF0000U) >> 16U); in sdmmc_decode_scr()
34 scr->flags |= SD_SCR_SPEC3; in sdmmc_decode_scr()
36 scr->sd_ext_sec = (uint8_t)((raw_scr[0U] & 0x7800U) >> 10U); in sdmmc_decode_scr()
37 scr->cmd_support = (uint8_t)(raw_scr[0U] & 0x3U); in sdmmc_decode_scr()
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/Zephyr-latest/drivers/ethernet/
DKconfig.nxp_s32_gmac1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
25 int "TX ring data buffer size"
29 Size, in bytes, of the TX data buffer. The size must be big enough to
30 store one complete Ethernet frame, and be a multiple of the data bus
31 width.
42 int "RX ring data buffer size"
46 Size, in bytes, of the RX data buffer. The size must be big enough to
47 store one complete Ethernet frame, and be a multiple of the data bus
48 width.
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
7 channel: Select channel for data transmitting
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 channel: Select channel for data transmitting
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display: enable-mipi-display {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
[all …]
/Zephyr-latest/boards/shields/rk043fn02h_ct/
Drk043fn02h_ct.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 int-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_LOW>;
32 width = <480>;
34 display-timings {
35 compatible = "zephyr,panel-timing";
36 hsync-len = <41>;
37 hfront-porch = <4>;
38 hback-porch = <8>;
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/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
[all …]
/Zephyr-latest/boards/shields/rk043fn66hs_ctg/
Drk043fn66hs_ctg.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 irq-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_HIGH>;
27 reset-gpios = <&nxp_i2c_touch_fpc 1 GPIO_ACTIVE_LOW>;
33 width = <480>;
35 display-timings {
36 compatible = "zephyr,panel-timing";
37 hsync-len = <4>;
38 hfront-porch = <8>;
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/Zephyr-latest/drivers/video/
Dov7670.c4 * SPDX-License-Identifier: Apache-2.0
23 struct i2c_dt_spec bus; member
185 #define OV7670_VIDEO_FORMAT_CAP(width, height, format) \ argument
187 .pixelformat = (format), .width_min = (width), .width_max = (width), \
213 /* Brightness Control, with signal -128 to +128, 0x00 is middle value */
216 /* Internal clock pre-scalar,F(internal clock) = F(input clock)/(Bit[5:0]+1) */
233 {OV7670_DNSTH, 0x00}, /* De-noise Strength */
260 /* config the output window data, this can be configed later */
268 /* AGC/AEC - Automatic Gain Control/Automatic exposure Control */
327 /* Histogram-based AEC/AGC Control */
[all …]
/Zephyr-latest/drivers/sdhc/
Drcar_mmc.c4 * SPDX-License-Identifier: Apache-2.0
39 * @brief Renesas MMC host controller driver data
109 struct mmc_rcar_data *data = dev->data; in rcar_mmc_reset_and_mask_irqs() local
124 k_sem_reset(&data->irq_xref_fin); in rcar_mmc_reset_and_mask_irqs()
138 * @retval -EINVAL: the dev pointer is NULL
145 return -EINVAL; in rcar_mmc_card_busy()
160 * @retval -ETIMEDOUT: timed out while tx/rx
161 * @retval -EIO: I/O error
162 * @retval -EILSEQ: communication out of sync
170 return -ETIMEDOUT; in rcar_mmc_check_errors()
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/Zephyr-latest/drivers/mipi_dbi/
DCMakeLists.txt3 # SPDX-License-Identifier: Apache-2.0
11 # Data bus width is used by the SDK driver and processes it as a compile time option
14 dt_prop(data_bus_width PATH "${flexio0_lcd}" PROPERTY "mipi-mode")
15 # Values for mipi-mode property are defined inside dt-bindings/mipi_dbi/mipi_dbi.h.
16 # We pass a define to the SDK driver if we are using 8-bit mode.

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