1#
2# Copyright (c) 2024 Charles Dias <charlesdias.cd@outlook.com>
3#
4# SPDX-License-Identifier: Apache-2.0
5#
6
7description: |
8    STMicroelectronics STM32 Digital Camera Memory Interface (DCMI).
9    Example of node configuration at board level:
10
11    &dcmi {
12      status = "okay";
13      sensor = <&ov2640>;
14      pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
15                  &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pe0 &dcmi_d3_pe1
16                  &dcmi_d4_pe4 &dcmi_d5_pd3 &dcmi_d6_pe5 &dcmi_d7_pe6>;
17      pinctrl-names = "default";
18      bus-width = <8>;
19      hsync-active = <0>;
20      vsync-active = <0>;
21      pixelclk-active = <1>;
22      capture-rate = <1>;
23      dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
24              STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS |
25              STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;
26
27      port {
28        dcmi_ep_in: endpoint {
29          remote-endpoint = <&ov2640_ep_out>;
30        };
31      };
32    };
33
34compatible: "st,stm32-dcmi"
35
36include: [base.yaml, pinctrl-device.yaml]
37
38properties:
39  interrupts:
40    required: true
41
42  sensor:
43    required: true
44    type: phandle
45    description: phandle of connected sensor device
46
47  bus-width:
48    type: int
49    required: true
50    enum:
51      - 8
52      - 10
53      - 12
54      - 14
55    default: 8
56    description: |
57      Number of data lines actively used, valid for the parallel busses.
58
59  hsync-active:
60    type: int
61    required: true
62    enum:
63      - 0
64      - 1
65    description: |
66      Polarity of horizontal synchronization (DCMI_HSYNC_Polarity).
67      0 Horizontal synchronization active Low.
68      1 Horizontal synchronization active High.
69
70      For example, if DCMI_HSYNC_Polarity is programmed active high:
71      When HSYNC is low, the data is valid.
72      When HSYNC is high, the data is not valid (horizontal blanking).
73
74  vsync-active:
75    type: int
76    required: true
77    enum:
78      - 0
79      - 1
80    description: |
81      Polarity of vertical synchronization (DCMI_VSYNC_Polarity).
82      0 Vertical synchronization active Low.
83      1 Vertical synchronization active High.
84
85      For example, if DCMI_VSYNC_Polarity is programmed active high:
86      When VSYNC is low, the data is valid.
87      When VSYNC is high, the data is not valid (vertical blanking).
88
89  pixelclk-active:
90    type: int
91    required: true
92    enum:
93      - 0
94      - 1
95    description: |
96      Polarity of pixel clock (DCMI_PIXCK_Polarity).
97      0 Pixel clock active on Falling edge.
98      1 Pixel clock active on Rising edge.
99
100  capture-rate:
101    type: int
102    enum:
103      - 1
104      - 2
105      - 4
106    default: 1
107    description: |
108      The DCMI can capture all frames or alternate frames. If it is not specified,
109      the default is all frames.
110      1 Capture all frames.
111      2 Capture alternate frames.
112      4 Capture one frame every 4 frames.
113
114  dmas:
115    required: true
116    description: |
117      phandle of DMA controller. The DMA controller should be compatible with
118      DMA channel specifier. Specifies a phandle reference to the dma controller,
119      the channel number, the slot number, channel configuration and finally features.
120
121      dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
122              STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS |
123              STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;
124