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/Zephyr-latest/dts/bindings/clock/
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
[all …]
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
[all …]
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
[all …]
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCM PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
[all …]
Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7RS devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
[all …]
Dst,stm32f3-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F3 Reset and Clock controller node.
6 Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f3-rcc"
11 include: st,stm32-rcc.yaml
14 adc12-prescaler:
17 - 0 # Synchronous mode
18 - 1 # not divided
19 - 2
[all …]
Dst,stm32f1-clock-mco.yaml4 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32f1-clock-mco"
10 STM32 F1 series Microcontroller Clock Output (MCO)
13 prescaler before the output. However, note that certain inputs of
14 the MCO are fitted with a fixed prescaler, making it possible to
20 pinctrl-0 = <&rcc_mco_pa8>;
21 pinctrl-names = "default";
25 Note: in the `clocks` property, the domain clock source cell should
26 use the value representing the base clock, regardless of whether or
27 not the selected input is fitted with a prescaler.
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCX PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
[all …]
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB0 Reset and Clock controller node for STM32WB0 devices
6 This node is in charge of the system clock ('SYSCLK') source
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
24 default frequency in Hz for clock output
26 slow-clock:
29 Slow clock source selection.
[all …]
Dst,stm32mp1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32MP1 Reset and Clock controller node.
6 On STM32MP1 platforms, clock control configuration is performed on A9 side.
8 clock-frequency (mlhclk_ck).
10 compatible: "st,stm32mp1-rcc"
13 - name: st,stm32-rcc.yaml
14 property-blocklist:
15 - ahb-prescaler
16 - apb1-prescaler
17 - apb2-prescaler
[all …]
Dst,stm32wl-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WL Reset and Clock controller node.
6 For more description confere st,stm32-rcc.yaml
8 compatible: "st,stm32wl-rcc"
11 - name: st,stm32wb-rcc.yaml
12 property-blocklist:
13 - ahb4-prescaler
14 - cpu2-prescaler
17 cpu2-prescaler:
20 - 1
[all …]
/Zephyr-latest/dts/bindings/counter/
Dandestech,atcpit100.yaml4 # SPDX-License-Identifier: Apache-2.0
21 clock-frequency:
24 description: channel clock source
26 prescaler:
30 The prescaler value defines the counter frequency
31 (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler
32 value could be in range [1 .. clock-frequency] and 1 means no prescaler
33 for the PIT clock-frequency.
35 Defaults to 1 to use the PIT clock-frequency as the counter frequency.
37 Setting the prescaler value if the system overhead is close to or
[all …]
Dnxp,lptmr.yaml2 # SPDX-License-Identifier: Apache-2.0
14 clock-frequency:
16 description: Counter clock frequency
18 prescaler:
22 clk-source:
27 Selects the clock to be used by the LPMTR prescaler/glitch filter.
28 In time counter mode, this field selects the input clock to the prescaler.
29 In pulse counter mode, this field selects the input clock to the glitch filter.
30 The clock connections vary by device, see the device reference manual for
33 input-pin:
[all …]
/Zephyr-latest/tests/drivers/counter/counter_basic_api/boards/
Dda1469x_dk_pro.overlay2 clock-src = <&lp_clk>;
3 prescaler = <1>;
8 clock-src = <&divn_clk>;
9 prescaler = <1>;
14 clock-src = <&lp_clk>;
15 prescaler = <2>;
20 clock-src = <&divn_clk>;
21 prescaler = <32>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/dts/bindings/timer/
Dadi,max32-timer.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-timer"
8 include: [base.yaml, reset-device.yaml]
17 clock-source:
21 Clock source to be used by the WDT peripheral. The following options
23 - 0: "ADI_MAX32_PRPH_CLK_SRC_PCLK" Peripheral clock
24 - 1: "ADI_MAX32_PRPH_CLK_SRC_EXTCLK" External Clock
25 - 2: "ADI_MAX32_PRPH_CLK_SRC_IBRO" Internal Baud Rate Oscillator
26 - 3: "ADI_MAX32_PRPH_CLK_SRC_ERFO" External Radio Frequency Oscillator
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dinfineon,xmc4xxx-ccu8-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
23 The CCU8 modules use the CCU clock source. Each slice applies
24 a separate prescaler to divide the clock. The clock divider is
[all …]
/Zephyr-latest/dts/bindings/adc/
Dst,stm32f1-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
9 Remove the st,adc-clock-source and st,adc-prescaler property.
10 See adc-prescaler property in st,stm32f1-rcc binding to configure ADC
11 prescaler.
13 compatible: "st,stm32f1-adc"
16 - name: st,stm32-adc.yaml
17 property-blocklist:
18 - st,adc-clock-source
19 - st,adc-prescaler
Dst,stm32-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-adc"
9 include: [adc-controller.yaml, pinctrl-device.yaml]
21 "#io-channel-cells":
24 st,adc-clock-source:
28 - "SYNC"
29 - "ASYNC"
31 Type of ADC clock source :
32 - "SYNC": derived from the bus clock.
33 - "ASYNC" : independent and asynchronous with the bus clock
[all …]
/Zephyr-latest/samples/boards/st/mco/
DREADME.rst1 .. zephyr:code-sample:: stm32_mco
2 :name: Master Clock Output (MCO)
3 :relevant-api: pinctrl_interface
5 Output an internal clock for external use by the application.
18 Make sure that the output clock is enabled in dts overlay file.
19 Depending on the stm32 serie, several clock source and prescaler are possible for each MCOx.
20 The clock source is set by the DTS among the possible values for each stm32 serie.
21 The prescaler is set by the DTS, through the property ``prescaler = <MCOx_PRE(MCO_PRE_DIV_n)>;``
23 See :zephyr_file:`dts/bindings/clock/st,stm32-clock-mco.yaml`
31 .. zephyr-app-commands::
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dpll_hse_100.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 clock-frequency = <DT_FREQ_M(100)>;
29 ahb-prescaler = <1>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
Dpll_hse_100_ahb_50.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 ahb-prescaler = <2>;
29 clock-frequency = <DT_FREQ_M(50)>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]

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