| /Zephyr-latest/dts/bindings/clock/ |
| D | nordic,nrf-lfclk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 nRF LFCLK (Low Frequency CLocK)
7 The LFCLK can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
10 LFCLK SYNTH mode is selected and the LFXO clock is not
11 available. The HFXO clock is used indirectly through
12 the FLL16M clock in BYPASS mode.
14 - LFXO: The LFXO clock is used as a clock source if the
15 LFCLK SYNTH mode is selected and the LFXO clock is
16 available. The LFXO clock is used indirectly through
[all …]
|
| D | nordic,nrf-fll16m.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The FLL16M can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
10 FLL16M mode is BYPASS, or if the FLL16M mode is
11 closed-loop and the LFXO clock is not available.
13 - LFXO: The LFXO clock is used as a clock source if the
14 FLL16M mode is closed-loop and the LFXO clock is
20 open-loop-accuracy-ppm = <20000>;
21 closed-loop-base-accuracy-ppm = <5000>;
23 clock-names = "hfxo", "lfxo";
[all …]
|
| D | st,stm32f3-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32F3 Reset and Clock controller node.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f3-rcc"
11 include: st,stm32-rcc.yaml
14 adc12-prescaler:
17 - 0 # Synchronous mode
18 - 1 # not divided
19 - 2
20 - 4
[all …]
|
| D | renesas,ra-cgc-subclk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA Sub-Clock
6 compatible: "renesas,ra-cgc-subclk"
8 include: fixed-clock.yaml
11 drive-capability:
15 - 0
16 - 1
17 - 2
18 - 3
20 Sub-Clock Oscillator Drive Capability Switching
[all …]
|
| D | nxp,kinetis-scg.yaml | 1 # Copyright (c) 2019-2021 Vestas Wind Systems A/S
2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP Kinetis SCG (System Clock Generator) IP node
6 compatible: "nxp,kinetis-scg"
8 include: [clock-controller.yaml, base.yaml]
14 sosc-mode:
16 description: system oscillator mode
18 "#clock-cells":
21 clock-cells:
22 - name
|
| D | silabs,series2-hfrcodpll.yaml | 1 compatible: "silabs,series2-hfrcodpll"
4 Silicon Labs HFRCODPLL peripheral (high-frequency RC oscillator with digital phase-locked loop).
5 Can be used as a free-running RC oscillator or with PLL lock to the crystal oscillators HFXO
7 the `dpll-*` options to desired values.
9 In PLL mode, `clock-frequency` represents the target PLL frequency.
10 In free-running mode, `clock-frequency` represents the HFRCO band to use.
12 include: fixed-clock.yaml
15 dpll-n:
18 dpll-m:
21 dpll-edge:
[all …]
|
| /Zephyr-latest/dts/bindings/counter/ |
| D | nxp,lptmr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 clock-frequency:
16 description: Counter clock frequency
22 clk-source:
27 Selects the clock to be used by the LPMTR prescaler/glitch filter.
28 In time counter mode, this field selects the input clock to the prescaler.
29 In pulse counter mode, this field selects the input clock to the glitch filter.
30 The clock connections vary by device, see the device reference manual for
33 input-pin:
36 When LPTMR is in Pulse mode, this value
[all …]
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
30 duty-cycle = <32768>;
[all …]
|
| /Zephyr-latest/soc/atmel/sam/common/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
11 bool "Use external crystal oscillator for slow clock"
14 the slow clock. Note that this adds a few seconds to boot time, as the
15 crystal needs to stabilize after power-up.
17 Says n if you do not need accurate and precise timers. The slow clock
21 bool "Use external crystal oscillator for main clock"
24 The main clock is being used to drive the PLL, and thus driving the
25 processor clock.
28 main clock. Note that this adds about a second to boot time, as the
29 crystal needs to stabilize after power-up.
[all …]
|
| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
30 prompt "Clock rate to use for SPI flash"
33 This selects the SPI clock frequency that will be used for loading
37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
58 prompt "Reading mode used by the SPI flash"
[all …]
|
| /Zephyr-latest/dts/bindings/i2s/ |
| D | nxp,mcux-i2s.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP mcux SAI-I2S controller
6 compatible: "nxp,mcux-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 dma-names:
20 nxp,tx-dma-channel:
25 nxp,rx-dma-channel:
30 nxp,tx-sync-mode:
32 description: tx sync mode
34 nxp,rx-sync-mode:
[all …]
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,stm32-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-qdec"
9 - name: base.yaml
10 - name: pinctrl-device.yaml
13 pinctrl-0:
16 pinctrl-names:
19 st,encoder-mode:
22 Set encoder mode.
24 0x1: Encoder mode 1 (Default)
25 0x2: Encoder mode 2
[all …]
|
| D | sensirion,shtcx.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <I2C_BITRATE_FAST>;
18 measure-mode = "normal";
19 clock-stretching;
25 include: [sensor-device.yaml, i2c-device.yaml]
28 measure-mode:
32 Specifies which measurement mode is used.
33 SHTC1 sensor only supports the normal measuremnt mode.
35 - "normal"
36 - "low-power"
[all …]
|
| /Zephyr-latest/soc/nuvoton/npcx/ |
| D | Kconfig | 1 # Nuvoton Cortex-M4 Embedded Controller
4 # SPDX-License-Identifier: Apache-2.0
44 prompt "Clock rate to use for SPI flash"
47 This selects the max clock rate that will be used for loading firmware
51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
76 prompt "Reading mode used by the SPI flash"
[all …]
|
| /Zephyr-latest/dts/bindings/sdhc/ |
| D | zephyr,sdhc-spi-slot.yaml | 3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
16 spi-clock-mode-cpol:
19 Clock polarity to use for SPI SDHC. Some cards respond properly
20 only when the clock goes low when not active.
22 spi-clock-mode-cpha:
25 Clock phase: this dictates when is the data captured, and depends
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
[all …]
|
| /Zephyr-latest/dts/bindings/power/ |
| D | st,stm32wb0-pwr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32wb0-pwr"
8 include: "st,stm32-pwr.yaml"
11 smps-mode:
15 SMPS mode selection
18 - SMPS converter disabled
19 - LDOs supply voltage: VDD
22 'SMPS supply configuration', so this mode should NEVER be
23 selected on these boards. Only use this mode if your board
29 - SMPS converter enabled - clock disabled
[all …]
|
| /Zephyr-latest/drivers/entropy/ |
| D | Kconfig.stm32 | 4 # SPDX-License-Identifier: Apache-2.0
15 a entropy 32-bit value to the host when read. It is available for
21 int "Thread-mode random number pool size"
26 hardware to make them ready for thread mode consumers.
30 int "Thread-mode random number pool low-water threshold"
33 Low water-mark threshold in bytes to trigger entropy generation for
34 thread mode consumers. As soon as the number of available bytes in the
39 int "ISR-mode random number pool size"
48 int "ISR-mode random number pool low-water threshold"
51 Low water-mark threshold in bytes to trigger entropy generation for
[all …]
|
| /Zephyr-latest/dts/bindings/wifi/ |
| D | nordic,nrf70-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: This is a representation of the nRF70 Wi-Fi chip.
8 on-bus: qspi
11 qspi-frequency:
15 Maximum clock speed (in Hz) supported by the device.
20 qspi-quad-mode:
23 If specified, Use QSPI in quad mode (4 IO lines) otherwise in
24 SPI mode (2 IO lines - MOSI & MISO).
26 qspi-rx-delay:
30 Number of clock cycles from the rising edge of the SPI clock
[all …]
|
| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | renesas,smartbond-nor-psram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
59 erase-cs-idle-min-ns:
[all …]
|
| D | st,stm32-fmc-sdram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
28 refresh-rate = <603>;
33 st,sdram-control = <STM32_FMC_SDRAM_NC_9
41 st,sdram-timing = <2 6 4 6 2 2 2>;
51 Note that you will find definitions for the st,sdram-control field at
52 dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
[all …]
|
| /Zephyr-latest/soc/st/stm32/stm32l5x/ |
| D | power.c | 4 * SPDX-License-Identifier: Apache-2.0
23 /* select MSI as wake-up system clock if configured, HSI otherwise */
38 /* ensure the proper wake-up system clock */ in pm_state_set()
42 case 1: /* this corresponds to the STOP0 mode: */ in pm_state_set()
43 /* enter STOP0 mode */ in pm_state_set()
46 case 2: /* this corresponds to the STOP1 mode: */ in pm_state_set()
47 /* enter STOP1 mode */ in pm_state_set()
50 case 3: /* this corresponds to the STOP2 mode: */ in pm_state_set()
54 /* enter STOP2 mode */ in pm_state_set()
58 LOG_DBG("Unsupported power state substate-id %u", in pm_state_set()
[all …]
|
| /Zephyr-latest/soc/st/stm32/stm32l4x/ |
| D | power.c | 4 * SPDX-License-Identifier: Apache-2.0
23 /* select MSI as wake-up system clock if configured, HSI otherwise */
32 /* ensure the proper wake-up system clock */ in set_mode_stop()
36 case 1: /* this corresponds to the STOP0 mode: */ in set_mode_stop()
37 /* enter STOP0 mode */ in set_mode_stop()
40 case 2: /* this corresponds to the STOP1 mode: */ in set_mode_stop()
41 /* enter STOP1 mode */ in set_mode_stop()
44 case 3: /* this corresponds to the STOP2 mode: */ in set_mode_stop()
48 /* enter STOP2 mode */ in set_mode_stop()
52 LOG_DBG("Unsupported power state substate-id %u", substate_id); in set_mode_stop()
[all …]
|
| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.stm32_lptim | 4 # SPDX-License-Identifier: Apache-2.0
6 DT_CHOSEN_STDBY_TIMER := st,lptim-stdby-timer
17 and provides the standard "system clock driver" interfaces.
22 prompt "LPTIM clock value configuration"
24 This option is deprecated and configuration of LPTIM domain clock
30 Use LSI as LPTIM clock
35 Use LSE as LPTIM clock
54 depending on LPTIM input clock:
55 - LSI(32KHz): 4000 ticks/sec
56 - LSE(32678): 4096 ticks/sec
[all …]
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_s32z27x_rtu0_r52.dtsi | 2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 /delete-node/ cpu@4;
13 /delete-node/ cpu@5;
14 /delete-node/ cpu@6;
15 /delete-node/ cpu@7;
19 /* Accessing code RAM over AXIF - a read-only flash memory bus */
21 compatible = "mmio-sram";
26 compatible = "nxp,s32-sys-timer";
29 clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
[all …]
|
| D | nxp_s32z27x_rtu1_r52.dtsi | 2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 /delete-node/ cpu@0;
13 /delete-node/ cpu@1;
14 /delete-node/ cpu@2;
15 /delete-node/ cpu@3;
19 /* Accessing code RAM over AXIF - a read-only flash memory bus */
21 compatible = "mmio-sram";
26 compatible = "nxp,s32-sys-timer";
29 clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
[all …]
|
