Lines Matching +full:clock +full:- +full:mode

2 # SPDX-License-Identifier: Apache-2.0
20       pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25           power-up-delay = <100>;
26           num-auto-refresh = <8>;
27           mode-register = <0x220>;
28           refresh-rate = <603>;
33               st,sdram-control = <STM32_FMC_SDRAM_NC_9
41               st,sdram-timing = <2 6 4 6 2 2 2>;
51   Note that you will find definitions for the st,sdram-control field at
52   dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
59       compatible = "zephyr,memory-region", "mmio-sram";
62       zephyr,memory-region = "SDRAM1";
66       compatible = "zephyr,memory-region", "mmio-sram";
69       zephyr,memory-region = "SDRAM2";
76 compatible: "st,stm32-fmc-sdram"
81   "#address-cells":
85   "#size-cells":
89   power-up-delay:
92     description: Power-up delay in microseconds.
94   num-auto-refresh:
97     description: Number of auto-refresh commands issued.
99   mode-register:
103       A 14-bit field that defines the SDRAM Mode Register content. The mode
104       register bits are also used to program the extended mode register for
107   refresh-rate:
111       A 13-bit field defines the refresh rate of the SDRAM device. It is
112       expressed in number of memory clock cycles. It must be set at least to
113       41 SDRAM clock cycles.
115 child-binding:
123     st,sdram-control:
129         - NC: Number of bits of a column address.
130         - NR: Number of bits of a row address.
131         - MWID: Memory device width.
132         - NB: Number of internal banks.
133         - CAS: SDRAM CAS latency in number of memory clock cycles.
134         - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
136         - RBURST: Enable burst read mode. If two SDRAM devices are used both
138         - RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
142     st,sdram-timing:
148         - TMRD: Delay between a Load Mode Register command and an Active or
149           Refresh command in number of memory clock cycles.
150         - TXSR: Delay from releasing the Self-refresh command to issuing the
151           Activate command in number of memory clock cycles. If two SDRAM
154         - TRAS: Minimum Self-refresh period in number of memory clock cycles.
155         - TRC: Delay between the Refresh command and the Activate command, as
157           expressed in number of memory clock cycles. If two SDRAM devices are
160         - TWP: Delay between a Write and a Precharge command in number of memory
161           clock cycles
162         - TRP: Delay between a Precharge command and another command in number
163           of memory clock cycles. If two SDRAM devices are used, the TRP must be
165         - TRCD: Delay between the Activate command and a Read/Write command in
166           number of memory clock cycles.