Lines Matching +full:clock +full:- +full:mode

5 # SPDX-License-Identifier: Apache-2.0
18 	  Boot-ROM. Use the full Microchip SPI image generator program for
19 	  authentication and all other Boot-ROM loader features. Refer to the MCHP
30 	prompt "Clock rate to use for SPI flash"
33 	  This selects the SPI clock frequency that will be used for loading
37 	bool "SPI flash clock rate of 12 MHz"
40 	bool "SPI flash clock rate of 16 MHz"
43 	bool "SPI flash clock rate of 24 MHz"
46 	bool "SPI flash clock rate of 48 MHz"
58 	prompt "Reading mode used by the SPI flash"
61 	  This sets the reading mode that can be used by the SPI flash.
65 	bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 	bool "SPI flash operates full-duplex with fast reading mode"
71 	bool "SPI flash operates with dual data reading mode"
74 	bool "SPI flash operates with quad data reading mode"
178 	  slew rate which is 1/2 the AHB clock rate. Fast slew is the
179 	  AHB clock rate.
195 	int "Flash SPI Mode"
199 	  This three bit value corresponds to the QMSPI controllers clock idle and
201 	  to the data sheet. Default value is 0 corresponding to SPI Mode 0
203 	  Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
204 	  Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
227 		  or other non-JTAG alternate functions.
232 		  JTAG port in SWD mode.
237 		  JTAG port is enabled in SWD mode.
245 	  Select tracing mode for debug interface
250 		  JTAG port in SWD mode and ETM as tracing method.
251 		  ETM re-assigns 5 pins for clock and 4-bit data bus.
257 		  JTAG port in SWD mode and SWV as tracing method.
261 # common processor clock divider configuration
267 	  This divisor defines a ratio between processor clock (HCLK)
268 	  and main 96 MHz clock (MCK):