Lines Matching +full:clock +full:- +full:mode

4 # SPDX-License-Identifier: Apache-2.0
11 	bool "Use external crystal oscillator for slow clock"
14 	  the slow clock. Note that this adds a few seconds to boot time, as the
15 	  crystal needs to stabilize after power-up.
17 	  Says n if you do not need accurate and precise timers. The slow clock
21 	bool "Use external crystal oscillator for main clock"
24 	  The main clock is being used to drive the PLL, and thus driving the
25 	  processor clock.
28 	  main clock. Note that this adds about a second to boot time, as the
29 	  crystal needs to stabilize after power-up.
45 	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
50 	  the main clock frequency.
58 	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
64 	  the main clock frequency.
72 	  This divisor defines a ratio between processor clock (HCLK)
73 	  and master clock (MCK) where the maximum value is 150MHz:
80 	bool "CPU goes to Wait mode instead of Sleep mode"
84 	  For JTAG debugging CPU clock (HCLK) should not stop. In order to
85 	  achieve this, make CPU go to Wait mode instead of Sleep mode while
86 	  using external crystal oscillator for main clock.
91 	  At reset ERASE pin is configured in System IO mode. Asserting the
93 	  option will switch the pin to general IO mode giving control of the