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/Zephyr-latest/dts/bindings/sdhc/
Dnxp,imx-usdhc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-usdhc"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 data-timeout:
20 read-watermark:
26 write-watermark:
41 pwr-gpios:
42 type: phandle-array
45 This pin defaults to active high when consumed by the SD card. The
49 cd-gpios:
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Drenesas,ra-sdhc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-sdhc"
9 include: [sdhc.yaml, pinctrl-device.yaml]
16 bus-width:
19 - 1
20 - 4
23 sd-support:
26 mmc-support:
29 card-detect:
32 write-protect:
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/Zephyr-latest/dts/bindings/mmc/
Drenesas,rcar-emmc.yaml1 description: Renesas R-Car eMMC
3 compatible: "renesas,rcar-mmc"
5 include: [sdhc.yaml, mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 max-bus-freq:
23 non-removable:
26 Non-removable slots (like eMMC), which are assumed to always be present,
30 mmc-sdr104-support:
33 cd-gpios:
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Dst,stm32-sdmmc.yaml3 compatible: "st,stm32-sdmmc"
5 include: [mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 cd-gpios:
24 type: phandle-array
25 description: Card Detect pin
27 pwr-gpios:
28 type: phandle-array
31 bus-width:
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/Zephyr-latest/drivers/sdhc/
Drcar_mmc_registers.h4 * SPDX-License-Identifier: Apache-2.0
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
28 /* Command arguments register for SD card */
46 /* The SD card response registers hold the response from the SD card */
53 * The SD card interrupt flag register 1 indicates the response end and access
54 * end in the command sequence. This register also indicates the card
55 * detect/write protect state.
58 #define RCAR_MMC_INFO1_CD BIT(5) /* state of card detect */
59 #define RCAR_MMC_INFO1_INSERT BIT(4) /* card inserted */
60 #define RCAR_MMC_INFO1_REMOVE BIT(3) /* card removed */
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Dimx_usdhc.c4 * SPDX-License-Identifier: Apache-2.0
101 struct usdhc_data *data = dev->data; in transfer_complete_cb()
104 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
106 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
108 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
110 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
112 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
119 struct usdhc_data *data = dev->data; in sdio_interrupt_cb()
121 if (data->sdhc_cb) { in sdio_interrupt_cb()
122 data->sdhc_cb(dev, SDHC_INT_SDIO, data->sdhc_cb_user_data); in sdio_interrupt_cb()
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Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
48 /* mask for card current state */
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
109 * Whether the card supports HS or not can be determined using TRAN_SPEED
110 * field of card's CSD register.
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Drcar_mmc.c4 * SPDX-License-Identifier: Apache-2.0
106 /* cleanup SD card interrupt flag register and mask their interrupts */
109 struct mmc_rcar_data *data = dev->data; in rcar_mmc_reset_and_mask_irqs()
124 k_sem_reset(&data->irq_xref_fin); in rcar_mmc_reset_and_mask_irqs()
136 * @retval 0 card is not busy
137 * @retval 1 card is busy
138 * @retval -EINVAL: the dev pointer is NULL
145 return -EINVAL; in rcar_mmc_card_busy()
160 * @retval -ETIMEDOUT: timed out while tx/rx
161 * @retval -EIO: I/O error
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Dsam_hsmci.c4 * SPDX-License-Identifier: Apache-2.0
80 const struct sam_hsmci_config *config = dev->config; in sam_hsmci_reset()
81 Hsmci *hsmci = config->base; in sam_hsmci_reset()
83 uint32_t mr = hsmci->HSMCI_MR; in sam_hsmci_reset()
84 uint32_t dtor = hsmci->HSMCI_DTOR; in sam_hsmci_reset()
85 uint32_t sdcr = hsmci->HSMCI_SDCR; in sam_hsmci_reset()
86 uint32_t cstor = hsmci->HSMCI_CSTOR; in sam_hsmci_reset()
87 uint32_t cfg = hsmci->HSMCI_CFG; in sam_hsmci_reset()
89 hsmci->HSMCI_CR = HSMCI_CR_SWRST; in sam_hsmci_reset()
90 hsmci->HSMCI_MR = mr; in sam_hsmci_reset()
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Dsdhc_cdns_ll.c3 * SPDX-License-Identifier: Apache-2.0
12 /* card busy and present */
26 #define CDNSMMC_ADDRESS_MASK (CONFIG_SDHC_BUFFER_ALIGNMENT - 1)
59 return -ENXIO; in sdhc_cdns_write_phy_reg()
71 return -ETIMEDOUT; in sdhc_cdns_wait_ics()
92 LOG_ERR("Card detection timeout"); in sdhc_cdns_card_present()
93 return -ETIMEDOUT; in sdhc_cdns_card_present()
101 /* Reset embedded card, turn off supply voltage */ in sdhc_cdns_vol_reset()
117 * with input value- mode sd_ds,
128 sdhc_cdns_combo_phy_reg->cp_clk_wr_delay = 0; in cdns_sdhc_set_sdmmc_params()
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/Zephyr-latest/tests/drivers/sdhc/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
20 /* Prepare IO settings for card */
115 * Verify that the driver can detect a present SD card
125 /* Card not in slot, test card insertion interrupt */ in ZTEST()
126 TC_PRINT("Waiting for card to be present in slot\n"); in ZTEST()
129 zassert_equal(ret, 0, "Could not install card insertion interrupt"); in ZTEST()
130 /* Wait for card insertion */ in ZTEST()
132 /* Delay now that card is in slot */ in ZTEST()
134 zassert_equal(ret, 0, "Card insertion interrupt did not fire"); in ZTEST()
137 zassert_equal(ret, 1, "Card is not reported as present, is one connected?"); in ZTEST()
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/Zephyr-latest/include/zephyr/drivers/
Dsdhc.h4 * SPDX-License-Identifier: Apache-2.0
37 #define SDHC_TIMEOUT_FOREVER (-1)
49 uint32_t response[4]; /*!< SD card response field */
90 * the SD card.
113 * to the bus. Cards start with legacy timing, but UHS-II cards can go up to
148 /*!< card operation voltage around 3.3v */
150 /*!< card operation voltage around 3.0v */
152 /*!< card operation voltage around 1.8v */
154 /*!< card operation voltage around 1.2v */
169 unsigned int bus_8_bit_support: 1; /**< 8-bit Support for embedded device */
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/Zephyr-latest/drivers/disk/
Dsdmmc_stm32.c4 * SPDX-License-Identifier: Apache-2.0
100 MMC_TypeDef *sdmmcx = priv->hsd.Instance; in stm32_sdmmc_fc_enable()
102 sdmmcx->CLKCR |= SDMMC_CLKCR_HWFC_EN; in stm32_sdmmc_fc_enable()
108 struct stm32_sdmmc_priv *priv = dev->data; in stm32_sdmmc_isr()
111 HAL_MMC_IRQHandler(&priv->hsd); in stm32_sdmmc_isr()
113 HAL_SD_IRQHandler(&priv->hsd); in stm32_sdmmc_isr()
122 priv->status = hsd->ErrorCode; \
124 k_sem_give(&priv->sync); \
146 (clock_control_subsys_t)&priv->pclken[1], in stm32_sdmmc_clock_enable()
149 return -EIO; in stm32_sdmmc_clock_enable()
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/Zephyr-latest/doc/releases/
Dmigration-guide-4.0.rst39 to define default flash and ram partitioning based on TF-M.
60 specify it using the west ``--runner`` or ``-r`` option. (:github:`75284`)
61 * ADC: Domain clock needs to be explicitly defined if property st,adc-clock-source = <ASYNC> is use…
85 Trusted Firmware-M
130 Chip variants with open-drain outputs (``mcp23x09``, ``mcp23x18``) now correctly reflect this in
134 * The ``power-domain`` property has been removed in favor of ``power-domains``.
136 ``power-domain-names`` is also available to optionally name each entry in
137 ``power-domains``. The number of cells in the ``power-domains`` property need
138 to be defined using ``#power-domain-cells``.
143 * For all STM32 ADC that selects an asynchronous clock through ``st,adc-clock-source`` property,
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Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
249 newly created informational-only callback struct :c:struct:`bt_conn_auth_info_cb`.
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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/Zephyr-latest/boards/ezurio/mg100/doc/
Dindex.rst10 (LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller,
11 full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulato…
24 The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU,
32 * :abbr:`I2C (Inter-Integrated Circuit)`
39 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
42 * :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)`
43 * :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)`
44 * :abbr:`SD Card`
55 +-----------+------------+----------------------+
58 | ADC | on-chip | adc |
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/Zephyr-latest/boards/nxp/mimxrt1160_evk/
Dmimxrt1160_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1166dvm6a-pinctrl.dtsi>
16 drive-strength = "high";
17 bias-pull-down;
18 slew-rate = "fast";
22 drive-strength = "high";
23 bias-pull-up;
24 slew-rate = "fast";
29 drive-strength = "high";
30 slew-rate = "fast";
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/Zephyr-latest/boards/st/stm32f469i_disco/doc/
Dindex.rst6 The STM32F469 Discovery kit features an ARM Cortex-M4 based STM32F469NI MCU
8 some highlights of the STM32F469I-DISCO board:
11 - STM32 microcontroller in BGA216 package
12 - On-board ST-LINK/V2-1 debugger/programmer, supporting USB reenumeration capability
13 - Flexible board power supply:
15 - ST-LINK/V2-1 USB connector
16 - User USB FS connector
17 - VIN from Arduino* compatible connectors
19 - Four user LEDs
20 - Two push-buttons: USER and RESET
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/Zephyr-latest/boards/espressif/esp_wrover_kit/doc/
Dindex.rst6 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
8 ESP-WROVER-KIT features the following integrated components:
10 - ESP32-WROVER-E module
11 - LCD screen
12 - MicroSD card slot
14 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
16 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
17 cost-effective.
26 For more information, check `ESP32-WROVER-E Datasheet`_ and `ESP32 Datasheet`_.
31 The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections.
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/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/doc/
Dmec172xmodular_assy6930.rst5 The MEC172x Modular Card ASSY6930 (Rev. B) is a development board to evaluate the
12 - MEC172x (MEC1723, MEC1727 and MEC1728) ARM Cortex-M4 Processor
13 - 416 KB RAM and 128 KB boot ROM
14 - UART1 using microUSB
15 - PECI interface 3.0
16 - FAN, PWM and TACHO pins
17 - 5 SMBus instances
18 - eSPI header
19 - VCI interface
20 - 1 hardware driven PS/2 ports
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/Zephyr-latest/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1176dvmaa-pinctrl.dtsi>
16 drive-strength = "high";
17 bias-pull-down;
18 slew-rate = "fast";
22 drive-strength = "high";
23 bias-pull-up;
24 slew-rate = "fast";
32 drive-strength = "high";
33 slew-rate = "fast";
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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dra8x1.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8.1-m.dtsi>
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
11 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m85";
23 #address-cells = <1>;
24 #size-cells = <1>;
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/Zephyr-latest/boards/microchip/mec15xxevb_assy6853/doc/
Dindex.rst10 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
18 - MEC1521HA0SZ ARM Cortex-M4 Processor
19 - 256 KB RAM and 64 KB boot ROM
20 - Keyboard interface
21 - ADC & GPIO headers
22 - UART0, UART1, and UART2
23 - FAN0, FAN1, FAN2 headers
24 - FAN PWM interface
25 - JTAG/SWD, ETM and MCHP Trace ports
26 - PECI interface 3.0
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/Zephyr-latest/boards/microchip/mec172xevb_assy6906/doc/
Dindex.rst14 - MEC172x ARM Cortex-M4 Processor
15 - 416 KB RAM and 128 KB boot ROM
16 - Keyboard interface
17 - ADC & GPIO headers
18 - UART0 and UART1
19 - FAN0, FAN1, FAN2 headers
20 - FAN PWM interface
21 - JTAG/SWD, ETM and MCHP Trace ports
22 - PECI interface 3.0
23 - I2C voltage translator
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