1 /*
2 * Copyright (c) 2020 Amarula Solutions.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32_sdmmc
8
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/disk.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/reset.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18 #include <soc.h>
19 #include <stm32_ll_rcc.h>
20
21 LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL);
22
23 #define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas)
24
25 #if STM32_SDMMC_USE_DMA
26 #include <zephyr/drivers/dma.h>
27 #include <zephyr/drivers/dma/dma_stm32.h>
28 #include <stm32_ll_dma.h>
29 #endif
30
31 #ifndef MMC_TypeDef
32 #define MMC_TypeDef SDMMC_TypeDef
33 #endif
34
35 #ifndef SDMMC_BUS_WIDE_1B
36 #define SDMMC_BUS_WIDE_1B SDIO_BUS_WIDE_1B
37 #endif
38
39 #ifndef SDMMC_BUS_WIDE_4B
40 #define SDMMC_BUS_WIDE_4B SDIO_BUS_WIDE_4B
41 #endif
42
43 #ifndef SDMMC_BUS_WIDE_8B
44 #define SDMMC_BUS_WIDE_8B SDIO_BUS_WIDE_8B
45 #endif
46
47 typedef void (*irq_config_func_t)(const struct device *dev);
48
49 #if STM32_SDMMC_USE_DMA
50
51 static const uint32_t table_priority[] = {
52 DMA_PRIORITY_LOW,
53 DMA_PRIORITY_MEDIUM,
54 DMA_PRIORITY_HIGH,
55 DMA_PRIORITY_VERY_HIGH
56 };
57
58 struct sdmmc_dma_stream {
59 const struct device *dev;
60 uint32_t channel;
61 uint32_t channel_nb;
62 DMA_TypeDef *reg;
63 struct dma_config cfg;
64 };
65 #endif
66
67 #ifdef CONFIG_SDMMC_STM32_EMMC
68 typedef MMC_HandleTypeDef HandleTypeDef;
69 typedef HAL_MMC_CardInfoTypeDef CardInfoTypeDef;
70 #else
71 typedef SD_HandleTypeDef HandleTypeDef;
72 typedef HAL_SD_CardInfoTypeDef CardInfoTypeDef;
73 #endif
74
75 struct stm32_sdmmc_priv {
76 irq_config_func_t irq_config;
77 struct k_sem thread_lock;
78 struct k_sem sync;
79 HandleTypeDef hsd;
80 int status;
81 struct k_work work;
82 struct gpio_callback cd_cb;
83 struct gpio_dt_spec cd;
84 struct gpio_dt_spec pe;
85 struct stm32_pclken *pclken;
86 const struct pinctrl_dev_config *pcfg;
87 const struct reset_dt_spec reset;
88
89 #if STM32_SDMMC_USE_DMA
90 struct sdmmc_dma_stream dma_rx;
91 struct sdmmc_dma_stream dma_tx;
92 DMA_HandleTypeDef dma_tx_handle;
93 DMA_HandleTypeDef dma_rx_handle;
94 #endif
95 };
96
97 #ifdef CONFIG_SDMMC_STM32_HWFC
stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv * priv)98 static void stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv *priv)
99 {
100 MMC_TypeDef *sdmmcx = priv->hsd.Instance;
101
102 sdmmcx->CLKCR |= SDMMC_CLKCR_HWFC_EN;
103 }
104 #endif
105
stm32_sdmmc_isr(const struct device * dev)106 static void stm32_sdmmc_isr(const struct device *dev)
107 {
108 struct stm32_sdmmc_priv *priv = dev->data;
109
110 #ifdef CONFIG_SDMMC_STM32_EMMC
111 HAL_MMC_IRQHandler(&priv->hsd);
112 #else
113 HAL_SD_IRQHandler(&priv->hsd);
114 #endif
115 }
116
117 #define DEFINE_HAL_CALLBACK(name) \
118 void name(HandleTypeDef *hsd) \
119 { \
120 struct stm32_sdmmc_priv *priv = CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); \
121 \
122 priv->status = hsd->ErrorCode; \
123 \
124 k_sem_give(&priv->sync); \
125 }
126
127 #ifdef CONFIG_SDMMC_STM32_EMMC
128 DEFINE_HAL_CALLBACK(HAL_MMC_TxCpltCallback);
129 DEFINE_HAL_CALLBACK(HAL_MMC_RxCpltCallback);
130 DEFINE_HAL_CALLBACK(HAL_MMC_ErrorCallback);
131 #else
132 DEFINE_HAL_CALLBACK(HAL_SD_TxCpltCallback);
133 DEFINE_HAL_CALLBACK(HAL_SD_RxCpltCallback);
134 DEFINE_HAL_CALLBACK(HAL_SD_ErrorCallback);
135 #endif
136
stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv * priv)137 static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
138 {
139 const struct device *clock;
140
141 /* HSI48 Clock is enabled through using the device tree */
142 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
143
144 if (DT_INST_NUM_CLOCKS(0) > 1) {
145 if (clock_control_configure(clock,
146 (clock_control_subsys_t)&priv->pclken[1],
147 NULL) != 0) {
148 LOG_ERR("Failed to enable SDMMC domain clock");
149 return -EIO;
150 }
151 }
152
153 if (IS_ENABLED(CONFIG_SDMMC_STM32_CLOCK_CHECK)) {
154 uint32_t sdmmc_clock_rate;
155
156 if (clock_control_get_rate(clock,
157 (clock_control_subsys_t)&priv->pclken[1],
158 &sdmmc_clock_rate) != 0) {
159 LOG_ERR("Failed to get SDMMC domain clock rate");
160 return -EIO;
161 }
162
163 if (sdmmc_clock_rate != MHZ(48)) {
164 LOG_ERR("SDMMC Clock is not 48MHz (%d)", sdmmc_clock_rate);
165 return -ENOTSUP;
166 }
167 }
168
169 /* Enable the APB clock for stm32_sdmmc */
170 return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]);
171 }
172
173 #if !defined(CONFIG_SDMMC_STM32_EMMC)
stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv * priv)174 static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
175 {
176 const struct device *clock;
177
178 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
179
180 return clock_control_off(clock,
181 (clock_control_subsys_t)&priv->pclken);
182 }
183 #endif
184
185 #if STM32_SDMMC_USE_DMA
186
stm32_sdmmc_dma_cb(const struct device * dev,void * arg,uint32_t channel,int status)187 static void stm32_sdmmc_dma_cb(const struct device *dev, void *arg,
188 uint32_t channel, int status)
189 {
190 DMA_HandleTypeDef *hdma = arg;
191
192 if (status != 0) {
193 LOG_ERR("DMA callback error with channel %d.", channel);
194
195 }
196
197 HAL_DMA_IRQHandler(hdma);
198 }
199
stm32_sdmmc_configure_dma(DMA_HandleTypeDef * handle,struct sdmmc_dma_stream * dma)200 static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma_stream *dma)
201 {
202 int ret;
203
204 if (!device_is_ready(dma->dev)) {
205 LOG_ERR("Failed to get dma dev");
206 return -ENODEV;
207 }
208
209 dma->cfg.user_data = handle;
210
211 ret = dma_config(dma->dev, dma->channel, &dma->cfg);
212 if (ret != 0) {
213 LOG_ERR("Failed to conig");
214 return ret;
215 }
216
217 handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb);
218 handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1;
219 handle->Init.PeriphInc = DMA_PINC_DISABLE;
220 handle->Init.MemInc = DMA_MINC_ENABLE;
221 handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
222 handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
223 handle->Init.Mode = DMA_PFCTRL;
224 handle->Init.Priority = table_priority[dma->cfg.channel_priority],
225 handle->Init.FIFOMode = DMA_FIFOMODE_ENABLE;
226 handle->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
227 handle->Init.MemBurst = DMA_MBURST_INC4;
228 handle->Init.PeriphBurst = DMA_PBURST_INC4;
229
230 return ret;
231 }
232
stm32_sdmmc_dma_init(struct stm32_sdmmc_priv * priv)233 static int stm32_sdmmc_dma_init(struct stm32_sdmmc_priv *priv)
234 {
235 int err;
236
237 LOG_DBG("using dma");
238
239 err = stm32_sdmmc_configure_dma(&priv->dma_tx_handle, &priv->dma_tx);
240 if (err) {
241 LOG_ERR("failed to init tx dma");
242 return err;
243 }
244 __HAL_LINKDMA(&priv->hsd, hdmatx, priv->dma_tx_handle);
245 HAL_DMA_Init(&priv->dma_tx_handle);
246
247 err = stm32_sdmmc_configure_dma(&priv->dma_rx_handle, &priv->dma_rx);
248 if (err) {
249 LOG_ERR("failed to init rx dma");
250 return err;
251 }
252 __HAL_LINKDMA(&priv->hsd, hdmarx, priv->dma_rx_handle);
253 HAL_DMA_Init(&priv->dma_rx_handle);
254
255 return err;
256 }
257
stm32_sdmmc_dma_deinit(struct stm32_sdmmc_priv * priv)258 static int stm32_sdmmc_dma_deinit(struct stm32_sdmmc_priv *priv)
259 {
260 int ret;
261 struct sdmmc_dma_stream *dma_tx = &priv->dma_tx;
262 struct sdmmc_dma_stream *dma_rx = &priv->dma_rx;
263
264 ret = dma_stop(dma_tx->dev, dma_tx->channel);
265 HAL_DMA_DeInit(&priv->dma_tx_handle);
266 if (ret != 0) {
267 LOG_ERR("Failed to stop tx DMA transmission");
268 return ret;
269 }
270 ret = dma_stop(dma_rx->dev, dma_rx->channel);
271 HAL_DMA_DeInit(&priv->dma_rx_handle);
272 if (ret != 0) {
273 LOG_ERR("Failed to stop rx DMA transmission");
274 return ret;
275 }
276 return ret;
277 }
278
279 #endif
280
stm32_sdmmc_access_init(struct disk_info * disk)281 static int stm32_sdmmc_access_init(struct disk_info *disk)
282 {
283 const struct device *dev = disk->dev;
284 struct stm32_sdmmc_priv *priv = dev->data;
285 int err;
286
287 if (priv->status == DISK_STATUS_NOMEDIA) {
288 return -ENODEV;
289 }
290
291 #if STM32_SDMMC_USE_DMA
292 err = stm32_sdmmc_dma_init(priv);
293 if (err) {
294 LOG_ERR("DMA init failed");
295 return err;
296 }
297 #endif
298
299 err = stm32_sdmmc_clock_enable(priv);
300 if (err) {
301 LOG_ERR("failed to init clocks");
302 return err;
303 }
304
305 err = reset_line_toggle_dt(&priv->reset);
306 if (err) {
307 LOG_ERR("failed to reset peripheral");
308 return err;
309 }
310
311 #ifdef CONFIG_SDMMC_STM32_EMMC
312 err = HAL_MMC_Init(&priv->hsd);
313 #else
314 err = HAL_SD_Init(&priv->hsd);
315 #endif
316 if (err != HAL_OK) {
317 LOG_ERR("failed to init stm32_sdmmc (ErrorCode 0x%X)", priv->hsd.ErrorCode);
318 return -EIO;
319 }
320
321 #ifdef CONFIG_SDMMC_STM32_HWFC
322 stm32_sdmmc_fc_enable(priv);
323 #endif
324
325 priv->status = DISK_STATUS_OK;
326 return 0;
327 }
328
stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv * priv)329 static int stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv *priv)
330 {
331 int err = 0;
332
333 #if STM32_SDMMC_USE_DMA
334 err = stm32_sdmmc_dma_deinit(priv);
335 if (err) {
336 LOG_ERR("DMA deinit failed");
337 return err;
338 }
339 #endif
340
341 #if defined(CONFIG_SDMMC_STM32_EMMC)
342 err = HAL_MMC_DeInit(&priv->hsd);
343 #else
344 err = HAL_SD_DeInit(&priv->hsd);
345 stm32_sdmmc_clock_disable(priv);
346 #endif
347 if (err != HAL_OK) {
348 LOG_ERR("failed to deinit stm32_sdmmc (ErrorCode 0x%X)", priv->hsd.ErrorCode);
349 return err;
350 }
351
352 priv->status = DISK_STATUS_UNINIT;
353 return 0;
354 }
355
stm32_sdmmc_access_status(struct disk_info * disk)356 static int stm32_sdmmc_access_status(struct disk_info *disk)
357 {
358 const struct device *dev = disk->dev;
359 struct stm32_sdmmc_priv *priv = dev->data;
360
361 return priv->status;
362 }
363
stm32_sdmmc_is_card_in_transfer(HandleTypeDef * hsd)364 static int stm32_sdmmc_is_card_in_transfer(HandleTypeDef *hsd)
365 {
366 #ifdef CONFIG_SDMMC_STM32_EMMC
367 return HAL_MMC_GetCardState(hsd) == HAL_MMC_CARD_TRANSFER;
368 #else
369 return HAL_SD_GetCardState(hsd) == HAL_SD_CARD_TRANSFER;
370 #endif
371 }
372
stm32_sdmmc_read_blocks(HandleTypeDef * hsd,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)373 static int stm32_sdmmc_read_blocks(HandleTypeDef *hsd, uint8_t *data_buf,
374 uint32_t start_sector, uint32_t num_sector)
375 {
376 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
377
378 #ifdef CONFIG_SDMMC_STM32_EMMC
379 return HAL_MMC_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector);
380 #else
381 return HAL_SD_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector);
382 #endif
383
384 #else
385
386 #ifdef CONFIG_SDMMC_STM32_EMMC
387 return HAL_MMC_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector);
388 #else
389 return HAL_SD_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector);
390 #endif
391
392 #endif
393 }
394
stm32_sdmmc_access_read(struct disk_info * disk,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)395 static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
396 uint32_t start_sector, uint32_t num_sector)
397 {
398 const struct device *dev = disk->dev;
399 struct stm32_sdmmc_priv *priv = dev->data;
400 int err;
401
402 k_sem_take(&priv->thread_lock, K_FOREVER);
403
404 err = stm32_sdmmc_read_blocks(&priv->hsd, data_buf, start_sector, num_sector);
405 if (err != HAL_OK) {
406 LOG_ERR("sd read block failed %d", err);
407 err = -EIO;
408 goto end;
409 }
410
411 k_sem_take(&priv->sync, K_FOREVER);
412
413 if (priv->status != DISK_STATUS_OK) {
414 LOG_ERR("sd read error %d", priv->status);
415 err = -EIO;
416 goto end;
417 }
418
419 while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) {
420 }
421
422 end:
423 k_sem_give(&priv->thread_lock);
424 return err;
425 }
426
stm32_sdmmc_write_blocks(HandleTypeDef * hsd,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)427 static int stm32_sdmmc_write_blocks(HandleTypeDef *hsd,
428 uint8_t *data_buf,
429 uint32_t start_sector, uint32_t num_sector)
430 {
431 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
432
433 #ifdef CONFIG_SDMMC_STM32_EMMC
434 return HAL_MMC_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector);
435 #else
436 return HAL_SD_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector);
437 #endif
438
439 #else
440
441 #ifdef CONFIG_SDMMC_STM32_EMMC
442 return HAL_MMC_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector);
443 #else
444 return HAL_SD_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector);
445 #endif
446
447 #endif
448 }
449
stm32_sdmmc_access_write(struct disk_info * disk,const uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)450 static int stm32_sdmmc_access_write(struct disk_info *disk,
451 const uint8_t *data_buf,
452 uint32_t start_sector, uint32_t num_sector)
453 {
454 const struct device *dev = disk->dev;
455 struct stm32_sdmmc_priv *priv = dev->data;
456 int err;
457
458 k_sem_take(&priv->thread_lock, K_FOREVER);
459
460 err = stm32_sdmmc_write_blocks(&priv->hsd, (uint8_t *)data_buf, start_sector, num_sector);
461 if (err != HAL_OK) {
462 LOG_ERR("sd write block failed %d", err);
463 err = -EIO;
464 goto end;
465 }
466
467 k_sem_take(&priv->sync, K_FOREVER);
468
469 if (priv->status != DISK_STATUS_OK) {
470 LOG_ERR("sd write error %d", priv->status);
471 err = -EIO;
472 goto end;
473 }
474
475 while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) {
476 }
477
478 end:
479 k_sem_give(&priv->thread_lock);
480 return err;
481 }
482
stm32_sdmmc_get_card_info(HandleTypeDef * hsd,CardInfoTypeDef * info)483 static int stm32_sdmmc_get_card_info(HandleTypeDef *hsd, CardInfoTypeDef *info)
484 {
485 #ifdef CONFIG_SDMMC_STM32_EMMC
486 return HAL_MMC_GetCardInfo(hsd, info);
487 #else
488 return HAL_SD_GetCardInfo(hsd, info);
489 #endif
490 }
491
stm32_sdmmc_access_ioctl(struct disk_info * disk,uint8_t cmd,void * buff)492 static int stm32_sdmmc_access_ioctl(struct disk_info *disk, uint8_t cmd,
493 void *buff)
494 {
495 const struct device *dev = disk->dev;
496 struct stm32_sdmmc_priv *priv = dev->data;
497 CardInfoTypeDef info;
498 int err;
499
500 switch (cmd) {
501 case DISK_IOCTL_GET_SECTOR_COUNT:
502 err = stm32_sdmmc_get_card_info(&priv->hsd, &info);
503 if (err != HAL_OK) {
504 return -EIO;
505 }
506 *(uint32_t *)buff = info.LogBlockNbr;
507 break;
508 case DISK_IOCTL_GET_SECTOR_SIZE:
509 err = stm32_sdmmc_get_card_info(&priv->hsd, &info);
510 if (err != HAL_OK) {
511 return -EIO;
512 }
513 *(uint32_t *)buff = info.LogBlockSize;
514 break;
515 case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
516 *(uint32_t *)buff = 1;
517 break;
518 case DISK_IOCTL_CTRL_SYNC:
519 /* we use a blocking API, so nothing to do for sync */
520 break;
521 case DISK_IOCTL_CTRL_INIT:
522 return stm32_sdmmc_access_init(disk);
523 case DISK_IOCTL_CTRL_DEINIT:
524 return stm32_sdmmc_access_deinit(priv);
525 default:
526 return -EINVAL;
527 }
528 return 0;
529 }
530
531 static const struct disk_operations stm32_sdmmc_ops = {
532 .init = stm32_sdmmc_access_init,
533 .status = stm32_sdmmc_access_status,
534 .read = stm32_sdmmc_access_read,
535 .write = stm32_sdmmc_access_write,
536 .ioctl = stm32_sdmmc_access_ioctl,
537 };
538
539 static struct disk_info stm32_sdmmc_info = {
540 .name = "SD",
541 .ops = &stm32_sdmmc_ops,
542 };
543
544
545 #ifdef CONFIG_SDMMC_STM32_EMMC
stm32_sdmmc_card_present(struct stm32_sdmmc_priv * priv)546 static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv)
547 {
548 return true;
549 }
550 #else /* CONFIG_SDMMC_STM32_EMMC */
551 /*
552 * Check if the card is present or not. If no card detect gpio is set, assume
553 * the card is present. If reading the gpio fails for some reason, assume the
554 * card is there.
555 */
stm32_sdmmc_card_present(struct stm32_sdmmc_priv * priv)556 static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv)
557 {
558 int err;
559
560 if (!priv->cd.port) {
561 return true;
562 }
563
564 err = gpio_pin_get_dt(&priv->cd);
565 if (err < 0) {
566 LOG_WRN("reading card detect failed %d", err);
567 return true;
568 }
569 return err;
570 }
571
stm32_sdmmc_cd_handler(struct k_work * item)572 static void stm32_sdmmc_cd_handler(struct k_work *item)
573 {
574 struct stm32_sdmmc_priv *priv = CONTAINER_OF(item,
575 struct stm32_sdmmc_priv,
576 work);
577
578 if (stm32_sdmmc_card_present(priv)) {
579 LOG_DBG("card inserted");
580 priv->status = DISK_STATUS_UNINIT;
581 } else {
582 LOG_DBG("card removed");
583 stm32_sdmmc_access_deinit(priv);
584 priv->status = DISK_STATUS_NOMEDIA;
585 }
586 }
587
stm32_sdmmc_cd_callback(const struct device * gpiodev,struct gpio_callback * cb,uint32_t pin)588 static void stm32_sdmmc_cd_callback(const struct device *gpiodev,
589 struct gpio_callback *cb,
590 uint32_t pin)
591 {
592 struct stm32_sdmmc_priv *priv = CONTAINER_OF(cb,
593 struct stm32_sdmmc_priv,
594 cd_cb);
595
596 k_work_submit(&priv->work);
597 }
598
stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv * priv)599 static int stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv *priv)
600 {
601 int err;
602
603 if (!priv->cd.port) {
604 return 0;
605 }
606
607 if (!gpio_is_ready_dt(&priv->cd)) {
608 return -ENODEV;
609 }
610
611 gpio_init_callback(&priv->cd_cb, stm32_sdmmc_cd_callback,
612 1 << priv->cd.pin);
613
614 err = gpio_add_callback(priv->cd.port, &priv->cd_cb);
615 if (err) {
616 return err;
617 }
618
619 err = gpio_pin_configure_dt(&priv->cd, GPIO_INPUT);
620 if (err) {
621 goto remove_callback;
622 }
623
624 err = gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_EDGE_BOTH);
625 if (err) {
626 goto unconfigure_pin;
627 }
628 return 0;
629
630 unconfigure_pin:
631 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
632 remove_callback:
633 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
634 return err;
635 }
636
stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv * priv)637 static int stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv *priv)
638 {
639 if (!priv->cd.port) {
640 return 0;
641 }
642
643 gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_MODE_DISABLED);
644 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
645 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
646 return 0;
647 }
648 #endif /* !CONFIG_SDMMC_STM32_EMMC */
649
stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv * priv)650 static int stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv *priv)
651 {
652 int err;
653
654 if (!priv->pe.port) {
655 return 0;
656 }
657
658 if (!gpio_is_ready_dt(&priv->pe)) {
659 return -ENODEV;
660 }
661
662 err = gpio_pin_configure_dt(&priv->pe, GPIO_OUTPUT_ACTIVE);
663 if (err) {
664 return err;
665 }
666
667 k_sleep(K_MSEC(50));
668
669 return 0;
670 }
671
stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv * priv)672 static int stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv *priv)
673 {
674 if (!priv->pe.port) {
675 return 0;
676 }
677
678 gpio_pin_configure_dt(&priv->pe, GPIO_DISCONNECTED);
679 return 0;
680 }
681
disk_stm32_sdmmc_init(const struct device * dev)682 static int disk_stm32_sdmmc_init(const struct device *dev)
683 {
684 struct stm32_sdmmc_priv *priv = dev->data;
685 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
686 int err;
687
688 if (!device_is_ready(clk)) {
689 LOG_ERR("clock control device not ready");
690 return -ENODEV;
691 }
692
693 if (!device_is_ready(priv->reset.dev)) {
694 LOG_ERR("reset control device not ready");
695 return -ENODEV;
696 }
697
698 /* Configure dt provided device signals when available */
699 err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT);
700 if (err < 0) {
701 return err;
702 }
703
704 priv->irq_config(dev);
705
706 /* Initialize semaphores */
707 k_sem_init(&priv->thread_lock, 1, 1);
708 k_sem_init(&priv->sync, 0, 1);
709
710 #if !defined(CONFIG_SDMMC_STM32_EMMC)
711 k_work_init(&priv->work, stm32_sdmmc_cd_handler);
712
713 err = stm32_sdmmc_card_detect_init(priv);
714 if (err) {
715 return err;
716 }
717 #endif
718
719 err = stm32_sdmmc_pwr_init(priv);
720 if (err) {
721 goto err_card_detect;
722 }
723
724 if (stm32_sdmmc_card_present(priv)) {
725 priv->status = DISK_STATUS_UNINIT;
726 } else {
727 priv->status = DISK_STATUS_NOMEDIA;
728 }
729
730 stm32_sdmmc_info.dev = dev;
731 err = disk_access_register(&stm32_sdmmc_info);
732 if (err) {
733 goto err_pwr;
734 }
735 return 0;
736
737 err_pwr:
738 stm32_sdmmc_pwr_uninit(priv);
739 err_card_detect:
740 #if !defined(CONFIG_SDMMC_STM32_EMMC)
741 stm32_sdmmc_card_detect_uninit(priv);
742 #endif
743 return err;
744 }
745
746 #if DT_NODE_HAS_STATUS_OKAY(DT_DRV_INST(0))
747
748 #if STM32_SDMMC_USE_DMA
749
750 #define SDMMC_DMA_CHANNEL_INIT(dir, dir_cap) \
751 .dev = DEVICE_DT_GET(STM32_DMA_CTLR(0, dir)), \
752 .channel = DT_INST_DMAS_CELL_BY_NAME(0, dir, channel), \
753 .channel_nb = DT_DMAS_CELL_BY_NAME( \
754 DT_DRV_INST(0), dir, channel), \
755 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
756 DT_PHANDLE_BY_NAME(DT_DRV_INST(0), dmas, dir)), \
757 .cfg = { \
758 .dma_slot = STM32_DMA_SLOT(0, dir, slot), \
759 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
760 STM32_DMA_CHANNEL_CONFIG(0, dir)), \
761 .dma_callback = stm32_sdmmc_dma_cb, \
762 .linked_channel = STM32_DMA_HAL_OVERRIDE, \
763 }, \
764
765
766 #define SDMMC_DMA_CHANNEL(dir, DIR) \
767 .dma_##dir = { \
768 COND_CODE_1(DT_INST_DMAS_HAS_NAME(0, dir), \
769 (SDMMC_DMA_CHANNEL_INIT(dir, DIR)), \
770 (NULL)) \
771 },
772
773 #else
774 #define SDMMC_DMA_CHANNEL(dir, DIR)
775 #endif
776
777 PINCTRL_DT_INST_DEFINE(0);
778
stm32_sdmmc_irq_config_func(const struct device * dev)779 static void stm32_sdmmc_irq_config_func(const struct device *dev)
780 {
781 IRQ_CONNECT(DT_INST_IRQN(0),
782 DT_INST_IRQ(0, priority),
783 stm32_sdmmc_isr, DEVICE_DT_INST_GET(0),
784 0);
785 irq_enable(DT_INST_IRQN(0));
786 }
787
788 #if DT_INST_PROP(0, bus_width) == 1
789 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_1B
790 #elif DT_INST_PROP(0, bus_width) == 4
791 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_4B
792 #elif DT_INST_PROP(0, bus_width) == 8
793 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_8B
794 #endif /* DT_INST_PROP(0, bus_width) */
795
796 static struct stm32_pclken pclken_sdmmc[] = STM32_DT_INST_CLOCKS(0);
797
798 static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = {
799 .irq_config = stm32_sdmmc_irq_config_func,
800 .hsd = {
801 .Instance = (MMC_TypeDef *)DT_INST_REG_ADDR(0),
802 .Init.BusWide = SDMMC_BUS_WIDTH,
803 #if DT_INST_NODE_HAS_PROP(0, clk_div)
804 .Init.ClockDiv = DT_INST_PROP(0, clk_div),
805 #endif
806 },
807 #if DT_INST_NODE_HAS_PROP(0, cd_gpios)
808 .cd = GPIO_DT_SPEC_INST_GET(0, cd_gpios),
809 #endif
810 #if DT_INST_NODE_HAS_PROP(0, pwr_gpios)
811 .pe = GPIO_DT_SPEC_INST_GET(0, pwr_gpios),
812 #endif
813 .pclken = pclken_sdmmc,
814 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
815 .reset = RESET_DT_SPEC_INST_GET(0),
816 SDMMC_DMA_CHANNEL(rx, RX)
817 SDMMC_DMA_CHANNEL(tx, TX)
818 };
819
820 DEVICE_DT_INST_DEFINE(0, disk_stm32_sdmmc_init, NULL,
821 &stm32_sdmmc_priv_1, NULL, POST_KERNEL,
822 CONFIG_SD_INIT_PRIORITY,
823 NULL);
824 #endif
825
