1.. zephyr:board:: mec172xevb_assy6906 2 3Overview 4******** 5 6The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the 7Microchip MEC172X series microcontrollers. This board needs to be mated with 8part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. 9MEC172x and MEC152x SPI image formats are not compatible with each other. 10 11Hardware 12******** 13 14- MEC172x ARM Cortex-M4 Processor 15- 416 KB RAM and 128 KB boot ROM 16- Keyboard interface 17- ADC & GPIO headers 18- UART0 and UART1 19- FAN0, FAN1, FAN2 headers 20- FAN PWM interface 21- JTAG/SWD, ETM and MCHP Trace ports 22- PECI interface 3.0 23- I2C voltage translator 24- 10 SMBUS headers 25- VCI interface 26- 1 Hardware Driven PS/2 Port 27- eSPI header 28- 2 Sockets for SPI NOR chips 29- One reset and VCC_PWRDGD pushbuttons 30- One external PCA9555 I/O port with jumper selectable I2C address. 31- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. 32- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. 33 34For more information about the SOC's please see `MEC172x Reference Manual`_ 35 36Supported Features 37================== 38 39The mec172xevb_assy6906 board configuration supports the following hardware 40features: 41 42+-----------+------------+-------------------------------------+ 43| Interface | Controller | Driver/Component | 44+===========+============+=====================================+ 45| NVIC | on-chip | nested vector interrupt controller | 46+-----------+------------+-------------------------------------+ 47| SYSTICK | on-chip | systick | 48+-----------+------------+-------------------------------------+ 49| UART | on-chip | serial port | 50+-----------+------------+-------------------------------------+ 51| GPIO | on-chip | gpio | 52+-----------+------------+-------------------------------------+ 53| I2C | on-chip | i2c | 54+-----------+------------+-------------------------------------+ 55| PINMUX | on-chip | pinmux | 56+-----------+------------+-------------------------------------+ 57| PS/2 | on-chip | ps2 | 58+-----------+------------+-------------------------------------+ 59| KSCAN | on-chip | kscan | 60+-----------+------------+-------------------------------------+ 61| TACH | on-chip | tachometer | 62+-----------+------------+-------------------------------------+ 63| RPMFAN | on-chip | Fan speed controller | 64+-----------+------------+-------------------------------------+ 65 66Other hardware features are not currently supported by Zephyr. 67 68The default configuration can be found in the 69:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. 70 71Connections and IOs 72=================== 73 74This evaluation board kit is comprised of the following HW blocks: 75 76- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ 77- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_ 78- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ 79 80System Clock 81============ 82 83The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the 84on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock 85control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in 86the references at the end of this document. 87 88Serial Port 89=========== 90 91UART1 is configured for serial logs. 92 93Jumper settings 94*************** 95 96Please follow the jumper settings below to properly demo this 97board. Advanced users may deviate from this recommendation. 98 99Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 100================================================= 101 102Power-related jumpers 103--------------------- 104 105If you wish to power from +5V power brick, then connect to barrel connector ``P1`` 106(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``. 107 108If you wish to power from micro-USB type A/B connector ``P2``, move the 109jumper to ``JP30 7-8``. 110 111 112.. note:: A single jumper is required in ``JP30``. 113 114+------+-------+-------+------+------+ 115| JP31 | JP158 | JP159 | JP40 | JP42 | 116+======+=======+=======+======+======+ 117| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 | 118+------+-------+-------+------+------+ 119 120+------+------+------+------+------+------+------+ 121| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 | 122+======+======+======+======+======+======+======+ 123| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 124+------+------+------+------+------+------+------+ 125 126+------+------+------+------+------+------+------+------+------+ 127| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 | 128+======+======+======+======+======+======+======+======+======+ 129| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 130+------+------+------+------+------+------+------+------+------+ 131 132+------+------+------+------+------+------+------+ 133| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 | 134+======+======+======+======+======+======+======+ 135| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 136+------+------+------+------+------+------+------+ 137 138These jumpers configure VCC Power good and nRESET_IN. 139 140+------------------+-------------+ 141| JP32 | JP33 | 142| (VCC Power good) | (nRESET_IN) | 143+==================+=============+ 144| 1-2 | 1-2 | 145+------------------+-------------+ 146 147Boot-ROM Straps 148--------------- 149 150These jumpers configure MEC172x Boot-ROM straps. 151 152+------------+--------------+-------------+-------------+---------------+ 153| JP1 | JP2 | JP3 | JP7 | JP160 | 154| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) | 155+============+==============+=============+=============+===============+ 156| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 | 157+------------+--------------+-------------+-------------+---------------+ 158 159``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples 160SHD SPI CS0# and if high, it loads code from SHD SPI. 161 162Peripheral Routing Jumpers 163-------------------------- 164 165Each column of the following table illustrates how to enable UART0, UART1, SHD SPI 166and SWD, respectively. 167 168+-------+-------+------+------+------+------+------+ 169| UART0 (P11) | 170+-------+-------+------+------+------+------+------+ 171| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 | 172+=======+=======+======+======+======+======+======+ 173| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 | 174+-------+-------+------+------+------+------+------+ 175| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 | 176+-------+-------+------+------+------+------+------+ 177| 8-9 | 8-9 | | | | | | 178+-------+-------+------+------+------+------+------+ 179| 11-12 | 11-12 | | | | | | 180+-------+-------+------+------+------+------+------+ 181| 14-15 | 14-15 | | | | | | 182+-------+-------+------+------+------+------+------+ 183| 17-18 | 17-18 | | | | | | 184+-------+-------+------+------+------+------+------+ 185| | 20-21 | | | | | | 186+-------+-------+------+------+------+------+------+ 187| | 23-24 | | | | | | 188+-------+-------+------+------+------+------+------+ 189 190+------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+ 191| UART1 | 192+---------------------------------------------------+-------------------------------------------+ 193| (P12) | (P2) | 194+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 195| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 | 196+======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+ 197| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 | 198+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 199| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 | 200+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 201| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 | 202+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 203| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 | 204+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 205| | | | 14-15 | | | | | | | | | | 206+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 207| | | | 17-18 | | | | | | | | | | 208+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ 209 210NOTE: The "Hello World" example outputs at ``UART1 P12`` . 211 212+----------------------+-------+--------+ 213| SHD_SPI | SWD | LED4-5 | 214+-------+------+-------+-------+--------+ 215| JP23 | JP25 | JP156 | J18 | JP21 | 216+=======+======+=======+=======+========+ 217| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 | 218+-------+------+-------+-------+--------+ 219| 8-9 | | | 11-12 | 16-17 | 220+-------+------+-------+-------+--------+ 221| 14-15 | | | | | 222+-------+------+-------+-------+--------+ 223| 17-18 | | | | | 224+-------+------+-------+-------+--------+ 225 226Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1 227================================================================= 228 229The jumper configuration explained above covers the base board. The ASSY 2306914 MEC172x CPU board provides capability for an optional, external 32KHz 231clock source. The card includes a 32KHz crystal oscillator. The card can 232also be configured to use an external 50% duty cycle 32KHz source on the 233XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable 234register to select the external source matching the jumper settings. If 235using the MEC172x internal silicon oscillator then the 32K jumper settings 236are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please 237refer to the schematic in reference section below. 238 239Parallel 32KHz crystal configuration 240------------------------------------ 241 242+-------+-------+ 243| JP1 | JP2 | 244+=======+=======+ 245| 1-2 | 2-3 | 246+-------+-------+ 247 248External 32KHz 50% duty cycle configuration 249------------------------------------------- 250 251+-------+-------+ 252| JP2 | JP3 | 253+=======+=======+ 254| NC | 1-2 | 255+-------+-------+ 256 257NOTE: ``JP121 3-4`` on base board also needs to be loaded. 258 259 260Programming and Debugging 261************************* 262 263Setup 264===== 265 266#. If you use Dediprog SF100 programmer, then setup it. 267 268 Windows version can be found at the `SF100 Product page`_. 269 270 Linux version source code can be found at `SF100 Linux GitHub`_. 271 Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. 272 For Linux please make sure that you copied ``60-dediprog.rules`` 273 from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) 274 then restart service using: 275 276 .. code-block:: console 277 278 $ udevadm control --reload 279 280 Add directory with program ``dpcmd`` (on Linux) 281 or ``dpcmd.exe`` (on Windows) to your ``PATH``. 282 283#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within 284 that directory. 285 286#. Make the image generation available for Zephyr, by making the tool 287 searchable by path, or by setting an environment variable 288 ``MEC172X_SPI_GEN``, for example: 289 290 .. code-block:: console 291 292 export MEC172X_SPI_GEN=<path to tool>/mec172x_spi_gen_lin_x86_64 293 294 Note that the tools for Linux and Windows have different file names. 295 296#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support. 297 If needed, a custom SPI image configuration file can be specified to override the 298 default one. 299 300 .. code-block:: console 301 302 export MEC172X_SPI_CFG=custom_spi_cfg.txt 303 304Wiring 305======== 306 307#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. 308 309 .. image:: spidongle_assy6791.jpg 310 :align: center 311 :alt: SPI DONGLE ASSY 6791 Connected 312 313#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip 314 ``U3``. Make sure that your programmer's offset is 0x0. 315 For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. 316 317 .. image:: dediprog_connector.jpg 318 :align: center 319 :alt: SF100 Connected 320 321 322 .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! 323 Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. 324 Wiring connection is described in the table below. 325 326 +------------+---------------+ 327 | Dediprog | Assy6791 | 328 | Connector | J6 Connector | 329 +============+===============+ 330 | VCC | 1 | 331 +------------+---------------+ 332 | GND | 2 | 333 +------------+---------------+ 334 | CS | 3 | 335 +------------+---------------+ 336 | CLK | 4 | 337 +------------+---------------+ 338 | MISO | 6 | 339 +------------+---------------+ 340 | MOSI | 5 | 341 +------------+---------------+ 342 343#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board 344 to your host computer using the RS232 cable. 345 346#. Apply power to the board via a micro-USB cable. 347 Configure this option by using a jumper between ``JP30 7-8``. 348 349 .. image:: jp30_power_options.jpg 350 :align: center 351 :alt: Power Connection 352 353Building 354======== 355 356#. Build :zephyr:code-sample:`hello_world` application as you would normally do. 357 358#. The file :file:`spi_image.bin` will be created if the build system 359 can find the image generation tool. This binary image can be used 360 to flash the SPI chip. 361 362Flashing 363======== 364 365#. Run your favorite terminal program to listen for output. 366 Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. 367 368 For example: 369 370 .. code-block:: console 371 372 $ minicom -D /dev/ttyUSB0 -o 373 374 The -o option tells minicom not to send the modem initialization 375 string. Connection should be configured as follows: 376 377 - Speed: 115200 378 - Data: 8 bits 379 - Parity: None 380 - Stop bits: 1 381 382#. Flash your board using ``west`` from the second terminal window. 383 Split first and second terminal windows to view both of them. 384 385 .. code-block:: console 386 387 $ west flash 388 389 .. note:: When west process started press Reset button ``S2`` and do not release it 390 till the whole west process will not be finished successfully. 391 392 .. image:: Reset_Button.jpg 393 :align: center 394 :alt: Reset Button 395 396 .. note:: If you don't want to press Reset button every time, you can disconnect 397 SPI Dongle ASSY 6791 from the EVB during the west flash programming. 398 Then connect it back to the ``J34`` header and apply power to the EVB. 399 Result will be the same. 400 401 402#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. 403 If you don't see this message, press the Reset button and the message should appear. 404 405Debugging 406========= 407 408This board comes with a Cortex ETM port which facilitates tracing and debugging 409using a single physical connection. In addition, it comes with sockets for 410JTAG only sessions. 411 412Troubleshooting 413=============== 414 415#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` 416 are lit. If one of these is off, then check the power-related jumpers again. 417 418#. If you can't program the board using Dediprog, disconnect the Assy6791 419 from the main board Assy6906 and try again. 420 421#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. 422 423PCA9555 Enabling 424================ 425#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: 426 427 As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, 428 however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, 429 so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use 430 I2C01 port by making some jumpers setting as below: 431 432 +---------+---------+------------------------------------------+ 433 | Pin 1 | Pin 2 | Comment | 434 +=========+=========+==========================================+ 435 | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | 436 +---------+---------+------------------------------------------+ 437 | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | 438 +---------+---------+------------------------------------------+ 439 | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | 440 +---------+---------+------------------------------------------+ 441 | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | 442 +---------+---------+------------------------------------------+ 443 | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | 444 +---------+---------+------------------------------------------+ 445 | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | 446 +---------+---------+------------------------------------------+ 447 | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | 448 +---------+---------+------------------------------------------+ 449 | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | 450 +---------+---------+------------------------------------------+ 451 452References 453********** 454 455.. target-notes:: 456 457.. _MEC172x Reference Manual: 458 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf 459.. _MEC172x EVB Schematic: 460 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf 461.. _MEC172x Daughter Card Schematic: 462 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-144WFBGA-Socket-DC-Assy6914-Rev-A-SCH.pdf 463.. _SPI Dongle Schematic: 464 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf 465.. _MEC172x SPI Image Gen: 466 https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen 467.. _SF100 Linux GitHub: 468 https://github.com/DediProgSW/SF100Linux 469.. _SF100 Product page: 470 https://www.dediprog.com/product/SF100 471.. _SF100 Linux manual: 472 https://www.dediprog.com/download/save/727.pdf 473
