Searched +full:bias +full:- +full:pull +full:- +full:pin +full:- +full:default (Results 1 – 25 of 57) sorted by relevance
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ti,cc32xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The TI CC32XX pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
8 on the pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
28 /* configuration for the uart0 "default" state */
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| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 Microchip XEC Pin controller Node
7 Based on pincfg-node.yaml binding.
8 The MCHP XEC pin controller is a singleton node responsible for controlling
9 pin function selection and pin properties. For example, you can use this
10 node to select peripheral pin functions.
19 All device pin configurations should be placed in child nodes of the
22 A group can also specify shared pin properties common to all the specified
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
24 supported standard pin properties:
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| D | microchip,mec5-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Microchip XEC Pin controller Node
6 Based on pincfg-node.yaml binding.
7 The MCHP XEC pin controller is a singleton node responsible for controlling
8 pin function selection and pin properties. For example, you can use this
9 node to select peripheral pin functions.
18 All device pin configurations should be placed in child nodes of the
21 A group can also specify shared pin properties common to all the specified
22 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
23 supported standard pin properties:
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| D | nordic,nrf-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The nRF pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* configuration for uart0 device, default state */
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
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| D | ti,cc13xx-cc26xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Device pin configuration should be placed in the child nodes of this node.
8 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
18 All device pin configurations should be placed in child nodes of the
22 supported standard pin properties:
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
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| D | gd,gd32-pinctrl-af.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The GD32 pin controller (AF model) is a singleton node responsible for
6 controlling pin function selection and pin properties. For example, you can
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
8 on the pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
28 /* configuration for the usart0 "default" state */
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| D | ene,kb1200-pinctrl.yaml | 1 # SPDX-License-Identifier: Apache-2.0
4 The ENE KB1200 pin controller is a singleton node responsible for controlling
5 pin function selection and pin properties. For example, you can use these
6 nodes to select peripheral pin functions.
8 Here is a list of supported standard pin properties:
9 - bias-disable: Disable pull-up/down resistor.
10 - bias-pull-up: Enable pull-up resistor.
11 - bias-pull-down: Enable pull-down resistor.
12 - drive-push-pull: Output driver is push-pull.
13 - drive-open-drain: Output driver is open-drain.
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| D | renesas,smartbond-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The SmartBond pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties, such as routing a UART RX to pin
7 P1.8 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
24 #include <dt-bindings/pinctrl/smartbond-pinctrl.h>
27 /* configuration for uart device, default state */
36 /* route UART RX to P0.8 and enable pull-up */
38 bias-pull-up;
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| D | nxp,mcux-rt-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30 bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
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| D | renesas,rcar-pfc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Renesas R-Car Pin Function Controller node
6 This binding gives a base representation of the R-Car pins configuration.
7 The R-Car pin controller is a singleton node responsible for controlling
8 pin function selection and pin properties. For example, you can use this
9 node to route CAN0 TX A to pin 'RD', and enable pull-up resistor as well
19 All device pin configurations should be placed in child nodes of the
21 /* You can put this in places like a board-pinctrl.dtsi file in
25 /* include pre-defined pins and functions for the SoC used by the board */
26 #include <dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
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| D | nxp,imx7d-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 bias-pull-up: PE=1, PS=<bias-pull-up-value index>
15 bias-pull-down: PE=1, PS=0
16 input-schmitt-enable: HYS=1
17 slew-rate: SRE=<enum idx>
18 drive-strength: DSE=<enum idx>
19 input-enable: SION=1 (in SW_PAD_CTL_MUX register)
21 If only required properties are supplied, the pin will have the following
26 SRE=<slew-rate>,
27 DSE=<drive-strength>,
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| D | telink,b91-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Telink B91 pin controller is a singleton node responsible for
6 controlling pin function selection and pin properties. For example, you can
7 use this node to route UART0 TX to pin PB2 and enable the pull-up resistor
8 on the pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined pins and functions for the SoC used by the board */
25 #include <dt-bindings/pinctrl/b91-pinctrl.h>
28 /* configuration for UART0 TX default state */
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| D | atmel,sam0-pinctrl.yaml | 2 # Copyright (c) 2021-2022, Gerson Fernando Budke
3 # SPDX-License-Identifier: Apache-2.0
8 The Atmel SAM0 pin controller is a singleton node responsible for controlling
9 pin function selection and pin properties. For example, you can use this node
10 to route SERCOM0 as UART were RX to pin PAD1 and enable the pull-up resistor
11 on the pin.
20 All device pin configurations should be placed in child nodes of the 'pinctrl'
23 /** You can put this in places like a <board>-pinctrl.dtsi file in
27 /** include pre-defined combinations for the SoC variant used by the board */
28 #include <dt-bindings/pinctrl/samr21g-pinctrl.h>
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| D | atmel,sam-pinctrl.yaml | 3 # Copyright (c) 2021-2022, Gerson Fernando Budke <nandojve@gmail.com>
4 # SPDX-License-Identifier: Apache-2.0
9 The Atmel SAM pin controller is a singleton node responsible for controlling
10 pin function selection and pin properties. For example, you can use this node
11 to route USART0 RX to pin PA10 and enable the pull-up resistor on the pin.
20 All device pin configurations should be placed in child nodes of the 'pinctrl'
23 /** You can put this in places like a <board>-pinctrl.dtsi file in
27 /** include pre-defined combinations for the SoC variant used by the board */
28 #include <dt-bindings/pinctrl/sam4sXc-pinctrl.h>
31 /* configuration for the usart0 "default" state */
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| D | raspberrypi,pico-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
28 /* configuration for the usart0 "default" state */
39 /* enable input on pin 1 */
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| D | pincfg-node.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Generic pin configuration schema
7 Many data items that are represented in a pin configuration node are
8 common and generic. Pin control bindings should use the properties
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
21 description: disable any pin bias
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
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| D | infineon,cat1-pinctrl.yaml | 4 # SPDX-License-Identifier: Apache-2.0
9 This is a singleton node responsible for controlling the pin function selection
10 and pin properties. For example, you can use this node to route
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
12 pin.
21 Pin configuration can also specify the pin properties, for example the
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
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| D | gd,gd32-pinctrl-afio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The GD32 pin controller (AFIO model) is a singleton node responsible for
6 controlling pin function selection and pin properties. For example, you can
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
8 on the pin. Remapping is also supported.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
28 /* configuration for the usart0 "default" state */
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| D | silabs,dbus-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8 pin. This pin controller is used for devices that use DBUS (Digital Bus)
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
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| D | nuvoton,npcx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Nuvoton pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use these
7 nodes to select peripheral pin functions.
9 Here is a list of supported standard pin properties:
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
14 Custom pin properties for npcx series are available also:
15 - pinmux-locked: Lock pinmux configuration for peripheral device
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| D | ite,it8xxx2-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The ITE IT8XXX2 pin controller is a node responsible for controlling
6 pin function selection and pin properties. For example, you can
8 function on the pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined pins and functions for the SoC used by the board */
25 #include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
28 /* configuration for I2C0 default state */
31 gpio-voltage = "1p8";
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| D | renesas,ra-pincrl-pfs.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Renesas RA pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a SCI0 RXD
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/renesas/pinctrl-ra.h>
27 /* configuration for the sci0 "default" state */
32 drive-strength = "medium";
41 The 'sci0_default' child node encodes the pin configurations for a
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
22 description: Remaps the PA11 pin to operate as PA9 pin.
25 remap-pa12:
27 description: Remaps the PA12 pin to operate as PA10 pin.
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| D | espressif,esp32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Espressif's pin controller is in charge of controlling pin configurations, pin
6 functionalities and pin properties as defined by pin states. In its turn, pin
7 states are composed by groups of pre-defined pin muxing definitions and user
8 provided pin properties.
10 Each Zephyr-based application has its own set of pin muxing/pin configuration
11 requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
12 could change a node's pin state properties. Though based on a particular board,
15 Suppose an application running on top of the ESP-WROVER-KIT board, for some
18 you'll notice that the I2C_0 node is already assigned to a pre-defined state.
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| /Zephyr-latest/dts/bindings/test/ |
| D | vnd,pinctrl-test.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Test pin controller.
7 compatible: "vnd,pinctrl-test"
11 child-binding:
13 Test pin controller pin configuration nodes. Each node is composed by one or
16 child-binding:
18 Test pin controller pin configuration group. Each group contains a list of
21 /* node representing default state for test_device0 */
27 /* both pins 0 and 1 have pull-up enabled */
28 bias-pull-up;
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