1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10
11  Note that the soc level iomuxc dts file can be examined to find the possible
12  pinmux options. Here are the affects of each property on the
13  IOMUXC SW_PAD_CTL register:
14  bias-pull-up: PE=1, PS=<bias-pull-up-value index>
15  bias-pull-down: PE=1, PS=0
16  input-schmitt-enable: HYS=1
17  slew-rate: SRE=<enum idx>
18  drive-strength: DSE=<enum idx>
19  input-enable: SION=1 (in SW_PAD_CTL_MUX register)
20
21  If only required properties are supplied, the pin will have the following
22  configuration:
23  HYS=0,
24  PS=0,
25  PE=0
26  SRE=<slew-rate>,
27  DSE=<drive-strength>,
28  SION=0,
29
30  Note that pins marked with LPSR can only have their PE and PS registers
31  configured
32
33
34compatible: "nxp,imx7d-pinctrl"
35
36include: base.yaml
37
38child-binding:
39  description: iMX pin controller pin group
40  child-binding:
41    description: |
42      iMX pin controller pin configuration node.
43
44    include:
45      - name: pincfg-node.yaml
46        property-allowlist:
47          - input-schmitt-enable
48          - input-enable
49          - bias-pull-up
50          - bias-pull-down
51
52    properties:
53      pinmux:
54        required: true
55        type: phandles
56        description: |
57          Pin mux selections for this group. See the soc level iomuxc DTSI file
58          for a defined list of these options.
59      drive-strength:
60        required: true
61        type: string
62        enum:
63          - "x1"
64          - "x4"
65          - "x2"
66          - "x6"
67        description: |
68          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
69      slew-rate:
70        required: true
71        type: string
72        enum:
73          - "fast"
74          - "slow"
75        description: |
76          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
77          0 FAST — Fast Frequency Slew Rate
78          1 SLOW — Slow Frequency Slew Rate
79      bias-pull-up-value:
80        type: string
81        default: "100k"
82        enum:
83          - "unused"
84          - "5k"
85          - "47k"
86          - "100k"
87        description: |
88          Select pull up resistor value. Sets PS field in IOMUXC peripheral.
89          Default of 100k as this is most common default register value for
90          SOC pads.
91          01: 5K- 5K pull up resistor
92          10: 47K- 47K pull up resistor
93          11: 100K- 100K pull up resistor
94