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/Zephyr-latest/dts/bindings/flash_controller/
Dgd,gd32-flash-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
7 GD32 FMC v1: its flash memory has 1 bank, page size is equal in the bank,
8 flash size is smaller than 512KB.
10 GD32 FMC v2: its flash memory has 2 banks. Page size equal within the same bank but
11 different between banks. Flash size can be up to 3072KB. FMC v2 has two
14 GD32 FMC v3: its flash memory has 2 banks, use sector size as the minimum operating
15 unit, the sector size is not equal.
17 compatible: "gd,gd32-flash-controller"
19 include: flash-controller.yaml
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v6_internal.h4 * SPDX-License-Identifier: Apache-2.0
16 * The size of the region is a 5-bit field, the three MSB bits are
18 * Together these fields specify the size of the region in bytes:
19 * 00000-00011 Reserved
29 * ------+------------+------+---+-----------+
30 * ... | SIZE[11:9] | ATTR | R | SIZE[1:0] |
31 * ------+------------+------+---+-----------+
33 /* arrange size into proper bit field in RDP aux reg*/
34 #define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \ argument
35 (((size - 1) & (BIT_MASK(3) << 2)) << 7))
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/Zephyr-latest/dts/bindings/memory-controllers/
Dnxp,flexram.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP FlexRAM on-chip ram controller
17 flexram,has-magic-addr:
24 flexram,num-ram-banks:
30 flexram,bank-size:
34 Size of each RAM bank in KB
36 flexram,bank-spec:
39 Custom mapping of runtime RAM bank partitions. If this
44 flexram,tcm-read-wait-mode:
49 flexram,tcm-write-wait-mode:
Dst,stm32-fmc-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
14 defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
15 bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
28 refresh-rate = <603>;
30 bank@0 {
33 st,sdram-control = <STM32_FMC_SDRAM_NC_9
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Dst,stm32-fmc-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
11 - 8 bits
12 - 16 bits
13 - 32 bits
15 - Asynchronous mode
16 - Burst mode for synchronous accesses with configurable option to split burst
18 - Multiplexed or non-multiplexed
20 - Asynchronous mode
21 - Burst mode for synchronous accesses
22 - Multiplexed or non-multiplexed
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Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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/Zephyr-latest/dts/bindings/gpio/
Dambiq,gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
23 gpio-map = <
30 #gpio-cells = <2>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "ambiq,gpio-bank";
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/Zephyr-latest/include/zephyr/dfu/
Dmcuboot.h5 * SPDX-License-Identifier: Apache-2.0
109 /** The size of the image, in bytes. */
145 * @brief Read the MCUboot image header information from an image bank.
150 * @param area_id flash_area ID of image bank which stores the image.
153 * @param header_size Size of the header structure passed by the caller.
259 * @brief Erase the image Bank.
261 * @param area_id flash_area ID of image bank to be erased.
267 * @brief Get the offset of the status in the image bank
269 * @param area_id flash_area ID of image bank to get the status offset
275 * @brief Get the offset of the status from an image bank size
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/Zephyr-latest/drivers/flash/
Dflash_stm32l4x.c6 * SPDX-License-Identifier: Apache-2.0
38 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
39 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
43 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
44 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
45 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
48 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
49 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
54 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
55 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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Dflash_stm32l5x.c4 * SPDX-License-Identifier: Apache-2.0
30 * so define it to flash size to avoid the unexptected check.
47 LOG_DBG("I-cache Disable"); in stm32_icache_disable()
51 CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in stm32_icache_disable()
60 if ((k_uptime_get_32() - tickstart) > in stm32_icache_disable()
66 status = -ETIMEDOUT; in stm32_icache_disable()
77 LOG_DBG("I-cache Enable"); in stm32_icache_enable()
83 int status = -EIO; in icache_wait_for_invalidate_complete()
93 if ((k_uptime_get_32() - tickstart) > in icache_wait_for_invalidate_complete()
102 LOG_DBG("I-cache Invalidation complete"); in icache_wait_for_invalidate_complete()
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Dflash_stm32h7x.c4 * SPDX-License-Identifier: Apache-2.0
41 #error Flash driver on M4 requires the DT property bank2-flash-size
52 /* When flash is dual bank and flash size is smaller than Max flash size of
60 int bank; member
71 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { in write_optb()
73 return -EIO; in write_optb()
76 if ((regs->OPTCR & mask) == value) { in write_optb()
87 regs->OPTCR = (regs->OPTCR & ~mask) | value; in write_optb()
89 regs->OPTCR |= FLASH_OPTCR_PG_OPT; in write_optb()
91 regs->OPTCR |= FLASH_OPTCR_OPTSTART; in write_optb()
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/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
11 /* All Banks, Offset 0xe: Bank Select Register */
13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
17 /* Bank 0, Offset 0x0: Transmit Control Register */
22 /* Bank 0, Offset 0x02: EPH status register */
26 /* Bank 0, Offset 0x4: Receive Control Register */
40 /* Bank 0, Offset 0x8: Memory information register */
42 #define MIR_SIZE_MASK GENMASK(7, 0) /* Memory size (2k pages) */
45 /* bank 0, offset 0xa: receive/phy control register */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
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Deth_enc28j60_priv.h1 /* ENC28J60 Stand-alone Ethernet Controller with SPI
5 * SPDX-License-Identifier: Apache-2.0
15 /* Any Bank Registers */
26 * Nibble 2 : Bank number
27 * Nibble 1-0: Register address
30 /* Bank 0 Registers */
56 /* Bank 1 Registers */
82 /* Bank 2 Registers */
102 /* Bank 3 Registers */
175 * - Unicast
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/Zephyr-latest/dts/bindings/mtd/
Dst,stm32-nv-flash.yaml4 "st,stm32-flash-controller" binding.
6 include: soc-nv-flash.yaml
8 compatible: st,stm32-nv-flash
11 max-erase-time:
13 description: max erase time(millisecond) of a flash sector or page or half-page
15 bank2-flash-size:
18 Embedded flash memory bank 2 size in KBytes.
19 Used by CM4 CPU because it cannot access flash controller register to read size.
20 Provides a way to configure this size when the flash controller driver runs on CM4 CPU.
/Zephyr-latest/arch/arc/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
38 v2 ISA for the ARC-HS & ARC-EM cores
66 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 floating-point extension
73 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 floating-point and double assist instructions
135 - LPcc instruction
136 - LP_COUNT core reg
137 - LP_START, LP_END aux regs
144 Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
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/Zephyr-latest/boards/wch/ch32v003evt/support/
Dopenocd.cfg5 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
9 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
10 $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
13 flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam0.c4 * SPDX-License-Identifier: Apache-2.0
32 /* The endpoint size stored in USB.PCKSIZE.SIZE */
80 UsbDevice *regs = &REGS->DEVICE; in usb_sam0_ep_isr()
81 UsbDeviceEndpoint *endpoint = &regs->DeviceEndpoint[ep]; in usb_sam0_ep_isr()
82 uint32_t intflag = endpoint->EPINTFLAG.reg; in usb_sam0_ep_isr()
84 endpoint->EPINTFLAG.reg = intflag; in usb_sam0_ep_isr()
88 data->ep_cb[0][ep](ep, USB_DC_EP_SETUP); in usb_sam0_ep_isr()
93 data->ep_cb[0][ep](ep, USB_DC_EP_DATA_OUT); in usb_sam0_ep_isr()
98 data->ep_cb[1][ep](ep | USB_SAM0_IN_EP, USB_DC_EP_DATA_IN); in usb_sam0_ep_isr()
100 if (data->addr != 0U) { in usb_sam0_ep_isr()
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/Zephyr-latest/boards/sifive/hifive_unleashed/support/
Dopenocd_hifive_unleashed.cfg4 ftdi_device_desc "Dual RS232-HS"
8 ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
11 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
20 $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
21 $_TARGETNAME.1 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
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/Zephyr-latest/boards/sifive/hifive_unmatched/support/
Dopenocd_hifive_unmatched.cfg4 ftdi_device_desc "Dual RS232-HS"
8 ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
11 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
20 $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
21 $_TARGETNAME.1 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
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/Zephyr-latest/boards/openisa/rv32m1_vega/support/
Dopenocd_rv32m1_vega_zero_riscy.cfg2 # SPDX-License-Identifier: BSD-3-Clause
20 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
23 target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
42 $_TARGETNAME configure -event gdb-detach {
46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
56 #define PFC_RCAR_DRIVE_STEP(size) \ argument
57 (size == 2 ? PFC_RCAR_DRIVE_MAX / 4 : PFC_RCAR_DRIVE_MAX / 8)
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr() local
77 uint8_t bank = 0; in pfc_rcar_set_gpsr()
81 bank * sizeof(uint32_t)); in pfc_rcar_set_gpsr()
88 pfc_rcar_write(pfc_base, PFC_RCAR_GPSR + bank * sizeof(uint32_t), val); in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
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/Zephyr-latest/boards/sifive/hifive1/support/
Dopenocd.cfg4 ftdi device_desc "Dual RS232-HS"
7 ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
10 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
13 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
14 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
16 flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
18 proc hifive1-load {file} {
23 proc hifive1-reset-halt {} {
27 proc hifive1-post-verify {} {
35 $_TARGETNAME configure -event gdb-attach {
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/Zephyr-latest/soc/espressif/esp32/
Dmemory.h3 * SPDX-License-Identifier: Apache-2.0
19 #define SRAM1_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START)
27 #define SRAM2_DRAM_USER_SIZE (SRAM2_DRAM_END - SRAM2_DRAM_USER_START)
33 * - 0x3ffae000 - 0x3ffb0000 (Reserved: data memory for ROM functions)
34 * - 0x3ffb0000 - 0x3ffe0000 (RAM bank 1 for application usage)
35 * - 0x3ffe0000 - 0x3ffe0440 (Reserved: data memory for ROM PRO CPU)
36 * - 0x3ffe3f20 - 0x3ffe4350 (Reserved: data memory for ROM APP CPU)
37 * - 0x3ffe4350 - 0x3ffe5230 (BT shm buffers)
38 * - 0x3ffe8000 - 0x3fffffff (RAM bank 2 for application usage)
50 #define SRAM1_IRAM_DRAM_CALC(addr_iram) (SRAM1_SIZE - (addr_iram - SRAM1_IRAM_START) + \
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