Lines Matching +full:bank +full:- +full:size
2 # SPDX-License-Identifier: Apache-2.0
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
23 gpio-map = <
30 #gpio-cells = <2>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "ambiq,gpio-bank";
37 gpio-controller;
38 #gpio-cells = <2>;
45 compatible = "ambiq,gpio-bank";
46 gpio-controller;
47 #gpio-cells = <2>;
54 compatible = "ambiq,gpio-bank";
55 gpio-controller;
56 #gpio-cells = <2>;
63 compatible = "ambiq,gpio-bank";
64 gpio-controller;
65 #gpio-cells = <2>;
73 provides the base register address 0x40010000. It has four "ambiq,gpio-bank"
76 address offset. The register address of pin described in gpio-cells can be
84 include: [gpio-nexus.yaml, base.yaml]